From 64c37303dc745c98a9e9f9821b80c7ad16d8cb31 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Albin=20Cor=C3=A9n?= <2108U9@gmail.com>
Date: Wed, 20 Feb 2019 17:52:16 +0100
Subject: [PATCH] Update README.md

---
 README.md | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/README.md b/README.md
index bc4b65e..920a01b 100644
--- a/README.md
+++ b/README.md
@@ -50,7 +50,6 @@ processor should probably be put into deepsleep indefinitely.
 ## Thread design:
 
 ### Thread flags:
-
 These bits should _under no circumstances_ be set manually. To change them,
 call the relevant exported routines.
 From LSB to MSB, the thread flag bits are as follows:
@@ -60,7 +59,6 @@ From LSB to MSB, the thread flag bits are as follows:
     **2-7:** Reserved
 
 ### Thread frame:
-
 Currently, the thread frame system consists of a single component: a pointer.
 The pointer points to the thread stack data. When a thread is first started, it
 contains (at least) a complete register mapping. The default mapping is that
@@ -74,7 +72,6 @@ are popped into their respective registers, as such, a fresh thread's *SP* will
 have the value *STACK_BASE*.
 
 ### Threading with other interrupts:
-
 As it stands, thread-switching will be postponed in the case that it is
 triggered during another ISR. As such, it is important that the system doesn't
 have large amounts of interrupts, as this may impede thread-switching.