From 026def0a26b07c40726b3e2e1fef7ce98a9231b6 Mon Sep 17 00:00:00 2001 From: GabrielTofvesson Date: Mon, 15 Oct 2018 09:27:23 +0200 Subject: [PATCH] Changed clock source for test callback module due to stability issues --- Callback.v | 4 ++-- SevenSegment.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Callback.v b/Callback.v index 210436e..d5d94c2 100644 --- a/Callback.v +++ b/Callback.v @@ -8,7 +8,7 @@ module Callback( parameter ISIZE; reg [ISIZE-1:0] counter; -reg [1:0] ctr_trigger = 2'b10; +reg [2:0] ctr_trigger = 2'b10; assign callback = !counter & ctr_trigger; @@ -18,7 +18,7 @@ always @(posedge clk or posedge reset) begin ctr_trigger <= 2'b10; end else if(counter) counter <= counter - 1'b1; - else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b01; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues + else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues end endmodule diff --git a/SevenSegment.v b/SevenSegment.v index 0f1deab..2249d73 100644 --- a/SevenSegment.v +++ b/SevenSegment.v @@ -84,8 +84,8 @@ ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags)); // Clock generator altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]); -// Callback module (generate timeouts) (Precision: 1/400M = 2.5ns) -Callback #(.ISIZE(32)) timeout(pll[3], 32'd400000000, ~value, cb); +// Callback module (generate timeouts) (Precision: 1/100M = 10ns) NOTE: 400MHz seems to be unstable, so a precision of 2.5ns comes at the price of stability +Callback #(.ISIZE(32)) timeout(pll[0], 32'd100000000, ~value, cb); // RAM module RAM main_memory(