diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..cb7cae8
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,26 @@
+# Quartus II gitignore
+greybox_tmp/*
+db/*
+incremental_db/*
+.git/*
+*.pof
+*.sof
+*.bak
+*.rpt
+*.pin
+*.sta
+*.sta.rpt
+*.sta.summary
+*.map
+*.map.rpt
+*.map.smsg
+*.map.summary
+*.cdf
+*.jdi
+*.done
+*.txt
+*.fit
+*.fit.summary
+*.qws
+*.qsf
+*.qpf
diff --git a/ALU.v b/ALU.v
new file mode 100644
index 0000000..602850c
--- /dev/null
+++ b/ALU.v
@@ -0,0 +1,154 @@
+module ALU(
+	input wire [7:0] a,
+	input wire [7:0] b,
+	input wire [7:0] op,
+	output wire [7:0] z,
+	output wire [7:0] o_flags
+);
+
+/*
+FLAGS:
+
+8'bHGFEDCBA
+
+A: Overflow
+B: Underflow
+C: CMP_GT
+D: CMP_EQ
+E: DIV_BY_0
+F: UNKNWN
+G: N/A
+H: N/A
+
+*/
+
+reg [15:0] i_z;
+reg [7:0] i_flg;
+
+assign z = i_z[7:0];
+assign o_flags = i_flg;
+
+always @* begin
+	case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
+		// ADD
+		0: begin
+			i_z <= a+b;
+			i_flg <= z < a ? 1 : 0; // Set overflow flag if necessary
+		end
+		
+		// SUB
+		1: begin
+			i_z <= a-b;
+			i_flg <= i_z[15] << 1;
+		end
+		
+		// MUL
+		2: begin
+			i_z <= a*b;
+			i_flg <= i_z[15:8] != 8'b00000000 ? 1 : 0;
+		end
+		
+		// DIV
+		3: begin
+			if(b != 8'b00000000) begin
+				i_z <= a/b;
+				i_flg <= 8'b00000000;
+			end else begin
+				i_z <= 8'b00000000;
+				i_flg <= 8'b00010000;
+			end
+		end
+		
+		// CMP
+		4: begin
+			/*
+			Flag bits:
+			
+			000 -> No output
+			001 -> a > b
+			010 -> a < b
+			011 -> No output
+			100 -> a == b
+			101 -> a >= b
+			110 -> a <= b
+			111 -> No output
+			
+			*/
+			i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 1 : 0;
+			i_flg <=
+					(a > b ? 4 : 0) | // a > b
+					(a == b ? 8 : 0); // a == b
+		end
+		
+		// AND
+		5: begin
+			i_z <= a & b;
+			i_flg <= 8'b00000000;
+		end
+		
+		// OR
+		6: begin
+			i_z <= a | b;
+			i_flg <= 8'b00000000;
+		end
+		
+		// XOR
+		7: begin
+			i_z <= a ^ b;
+			i_flg <= 8'b00000000;
+		end
+		
+		// NOT
+		8: begin
+			i_z <= ~a;
+			i_flg <= 8'b00000000;
+		end
+		
+		// NAND
+		9: begin
+			i_z <= ~(a & b);
+			i_flg <= 8'b00000000;
+		end
+		
+		// NOR
+		10: begin
+			i_z <= ~(a | b);
+			i_flg <= 8'b00000000;
+		end
+		
+		// XNOR
+		11: begin
+			i_z <= ~(a ^ b);
+			i_flg <= 8'b00000000;
+		end
+		
+		// CL_MUL
+		12: begin
+			i_z <=
+				(a[7] ? b << 7 : 0) ^
+				(a[6] ? b << 6 : 0) ^
+				(a[5] ? b << 5 : 0) ^
+				(a[4] ? b << 4 : 0) ^
+				(a[3] ? b << 3 : 0) ^
+				(a[2] ? b << 2 : 0) ^
+				(a[1] ? b << 1 : 0) ^
+				(a[0] ? b 		: 0);
+			
+			i_flg <=
+				(a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
+				(a[6] && (b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
+				(a[5] && (b[3] || b[4] || b[5] || b[6] || b[7])) ||
+				(a[4] && (b[4] || b[5] || b[6] || b[7])) ||
+				(a[3] && (b[5] || b[6] || b[7])) ||
+				(a[2] && (b[6] || b[7])) ||
+				(a[1] && b[7])
+				? 1 : 0;
+		end
+		default: begin
+			i_z <= 0;
+			i_flg <= 32; // Unknown opcode
+		end
+	endcase
+end
+
+endmodule
diff --git a/Divider.v b/Divider.v
new file mode 100644
index 0000000..4cabdb8
--- /dev/null
+++ b/Divider.v
@@ -0,0 +1,27 @@
+module Divider(
+	input wire clk,		// Clock input
+	output wire divided	// Divided output
+);
+
+// Parameters for division circuit
+parameter divideby = 1;
+parameter divide_reg_size;
+parameter pulsemode = 1;
+
+reg [divide_reg_size-1:0] div;	// Division counter
+reg div_int;							// Internal division result state
+
+assign divided = div_int;			// Assign internal result state to external output
+
+// Division
+always @ (posedge clk) begin
+	if(div == divideby) begin
+		div_int <= pulsemode ? 1 : ~div_int;
+		div <= 0;
+	end else begin
+		if(pulsemode) div_int <= 0;
+		div <= div + 1;
+	end
+end
+
+endmodule
diff --git a/FastAdder.v b/FastAdder.v
new file mode 100644
index 0000000..c9a31cf
--- /dev/null
+++ b/FastAdder.v
@@ -0,0 +1,37 @@
+module FastAdder4(
+	input wire c_in,
+	input wire [3:0] a,
+	input wire [3:0] b,
+	output wire [3:0] out,
+	output wire c_out
+);
+
+wire [3:0] gen = a & b; // Generator
+wire [3:0] prp = a ^ b;	// Propogator
+
+assign out = a ^ b ^ {
+	gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in),	// Carry 2
+	gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in),													// Carry 1
+	gen[0] | (prp[0] & c_in),																							// Carry 0
+	c_in																														// Carry -1 (in)
+};
+assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
+endmodule
+
+module FastAdder8(
+	input wire [WIRE_SIZE-1:0] a,
+	input wire [WIRE_SIZE-1:0] b,
+	output wire [WIRE_SIZE-1:0] out,
+	output wire c_out
+);
+
+parameter WIRE_SIZE;
+
+genvar i;
+generate
+	for(i=0; i<WIRE_SIZE; i = i + 1) begin
+		
+	end
+endgenerate
+
+endmodule
diff --git a/RAM.v b/RAM.v
new file mode 100644
index 0000000..48d7189
--- /dev/null
+++ b/RAM.v
@@ -0,0 +1,23 @@
+module RAM(
+	input wire clk,
+	output wire [10:0] RAM_addr,		// RAM address buffer
+	output wire RAM_A10,
+	output wire [1:0] RAM_bank_sel,	// RAM bank selection
+	inout wire [15:0] RAM_data,		// RAM data bus
+	output wire RAM_clk,					// RAM clock signal
+	output wire RAM_clk_enable,		// RAM enable clock
+	output wire RAM_enable,				// RAM chip enable
+	output wire RAM_strobe_row,		// RAM row strobe
+	output wire RAM_strobe_col,		// RAM column strobe
+	output wire RAM_write_enable,		// RAM data bus write enable
+	input wire read_rq,					// Read request (Internal)
+	input wire write_rq,					// Write request (Internal)
+	output reg [3:0] RAM_state,		// State information (Internal)
+	output wire op_trigger				// Event trigger wire
+);
+
+always @(posedge clk) begin
+	
+end
+
+endmodule
diff --git a/SDRAM.v b/SDRAM.v
new file mode 100644
index 0000000..4a837d6
--- /dev/null
+++ b/SDRAM.v
@@ -0,0 +1,5 @@
+module SDRAM_HY57V641620(
+	
+);
+
+endmodule
diff --git a/SegmentHexEncoder.v b/SegmentHexEncoder.v
new file mode 100644
index 0000000..31c4c4d
--- /dev/null
+++ b/SegmentHexEncoder.v
@@ -0,0 +1,24 @@
+module SegmentHexEncoder(
+	input wire [3:0] number,	// Binary number
+	output reg [7:0] encoded	// Encoded hex output
+);
+always @*
+	case(number)
+		0: encoded <= 8'hC0;
+		1: encoded <= 8'hF9;
+		2: encoded <= 8'hA4;
+		3: encoded <= 8'hB0;
+		4: encoded <= 8'h99;
+		5: encoded <= 8'h92;
+		6: encoded <= 8'h82;
+		7: encoded <= 8'hF8;
+		8: encoded <= 8'h80;
+		9: encoded <= 8'h98;
+		10: encoded <= 8'h88;
+		11: encoded <= 8'h83;
+		12: encoded <= 8'hC6;
+		13: encoded <= 8'hA1;
+		14: encoded <= 8'h86;
+		default: encoded <= 8'h8E;
+	endcase
+endmodule
diff --git a/SegmentManager.v b/SegmentManager.v
new file mode 100644
index 0000000..a82e561
--- /dev/null
+++ b/SegmentManager.v
@@ -0,0 +1,34 @@
+module SegmentManager(
+	input wire clk,						// 50MHz clock signal
+	input wire [7:0] segment_data0,	// Segment data for segment 0 (D1)
+	input wire [7:0] segment_data1,	// Segment data for segment 1 (D2)
+	input wire [7:0] segment_data2,	// Segment data for segment 2 (D3)
+	input wire [7:0] segment_data3,	// Segment data for segment 3 (D4)
+	output reg [3:0] segment_select,	// 7-segment display selector
+	output reg [7:0] segments			// Segment display bus
+);
+
+initial segment_select = 4'b1110;
+
+reg [1:0] seg_sel_track;	// Active display tracker
+
+wire clk_graphics;			// Internal clock divider output
+
+// Clock division circuit
+Divider #(.divideby(25000), .divide_reg_size(17)) divider_audio(clk, clk_graphics);	// Frequency: 50MHz/25k = 2kHz	TriggerType: Pulse
+
+// Change the active segment data
+always @(posedge clk_graphics) begin
+	segment_select <=(segment_select << 1) | segment_select[3];
+	seg_sel_track <= seg_sel_track + 1;
+end
+
+// Assign the active segment data to the segment bus
+always @*
+	case(seg_sel_track)
+		0: 		segments <= segment_data0;
+		1: 		segments <= segment_data1;
+		2: 		segments <= segment_data2;
+		default: segments <= segment_data3;
+	endcase
+endmodule
diff --git a/SevenSegment.v b/SevenSegment.v
new file mode 100644
index 0000000..b1582db
--- /dev/null
+++ b/SevenSegment.v
@@ -0,0 +1,139 @@
+module SevenSegment (
+	input wire latch, 					// S4
+	input wire next,						// S2
+	input wire value,						// S3
+	output reg [3:0] select_out, 		// LED1-LED4 [0-3]
+	input wire write,						// S1
+	input wire clk,						// 50MHz clock
+	output [3:0] seg_select,			// Q1-Q4      [0-3]
+	output [7:0] seg_write,				// a-g + dp   [0-7] + 8
+	output reg beep,						// Buzzer
+	output wire [10:0] RAM_addr,		// RAM address buffer
+	output wire RAM_A10,
+	output wire [1:0] RAM_bank_sel,	// RAM bank selection
+	inout wire [15:0] RAM_data,		// RAM data bus
+	output wire RAM_clk,					// RAM clock signal
+	output wire RAM_clk_enable,		// RAM enable clock
+	output wire RAM_enable,				// RAM chip enable
+	output wire RAM_strobe_row,		// RAM row strobe
+	output wire RAM_strobe_col,		// RAM column strobe
+	output wire RAM_write_enable		// RAM data bus write enable
+);
+
+// ----    SETTINGS    ---- //
+localparam PLL_SELECT = 4; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
+
+// ----    REGISTERS   ---- //
+reg debounce;							// Input debouncer
+reg db_trap;
+reg [3:0] seg_buf_numbers [0:3];	// 7-segment binary-number-representation buffer
+reg [1:0] stage;						// Computational stage
+reg [7:0] alu_a;
+reg [7:0] alu_b;
+reg [7:0] alu_op;
+
+// ----     WIRES      ---- //
+wire [7:0] seg_buf[0:3];			// Encoded segment buffer (8-bit expanded 4-bit number buffer)
+wire [7:0] alu_out;
+wire [7:0] alu_flags;
+wire [4:0] pll;
+
+assign pll[4] = clk;
+
+// ---- INITIAL VALUES ---- //
+initial select_out = 4'b1111;
+initial seg_buf_numbers[0] = 4'b0000;
+initial seg_buf_numbers[1] = 4'b0000;
+initial seg_buf_numbers[2] = 4'b0000;
+initial seg_buf_numbers[3] = 4'b0000;
+initial debounce = 0;
+
+// Hex encoders for each 4-bit input set. Generates an 8-bit hex output
+SegmentHexEncoder enc0(.number (seg_buf_numbers[0]), .encoded (seg_buf[0]));
+SegmentHexEncoder enc1(.number (seg_buf_numbers[1]), .encoded (seg_buf[1]));
+SegmentHexEncoder enc2(.number (seg_buf_numbers[2]), .encoded (seg_buf[2]));
+SegmentHexEncoder enc3(.number (seg_buf_numbers[3]), .encoded (seg_buf[3]));
+
+// A segment display manager to handle rendering data to the 7-segment displays
+SegmentManager seg_display(
+	.clk (clk), 
+	.segment_data0 (seg_buf[0]),
+	.segment_data1 (seg_buf[1]),
+	.segment_data2 (seg_buf[2]),
+	.segment_data3 (seg_buf[3]),
+	.segment_select (seg_select),
+	.segments (seg_write)
+);
+
+ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
+altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
+
+always @(posedge pll[PLL_SELECT]) begin
+	if(!latch && write && next) begin
+		debounce <= 1;
+	end
+	
+	if(write && next && db_trap) begin
+		debounce <= 0;
+		db_trap <= 0;
+	end
+	
+	if(!write && debounce && !db_trap) begin
+		db_trap <= 1;
+		if(stage == 0) begin
+			alu_a <= alu_a + 1;
+		end else if(stage == 1) begin
+			alu_b <= alu_b + 1;
+		end else if(stage == 2) begin
+			alu_op <= alu_op + 1;
+		end
+	end else if (!next && debounce && !db_trap) begin
+		db_trap <= 1;
+		stage <= stage + 1;
+		
+		if(stage == 2'b01) begin
+			seg_buf_numbers[0] <= 0;
+			seg_buf_numbers[1] <= 0;
+			seg_buf_numbers[2] <= 0;
+			seg_buf_numbers[3] <= 0;
+		end
+		else if(stage == 2'b10) begin
+			seg_buf_numbers[0] <= alu_out[7:4];
+			seg_buf_numbers[1] <= alu_out[3:0];
+			seg_buf_numbers[2] <= alu_flags[7:4];
+			seg_buf_numbers[3] <= alu_flags[3:0];
+		end
+		else if(stage == 2'b11) begin
+			seg_buf_numbers[0] <= alu_a[7:4];
+			seg_buf_numbers[1] <= alu_a[3:0];
+			seg_buf_numbers[2] <= alu_b[7:4];
+			seg_buf_numbers[3] <= alu_b[3:0];
+			alu_a <= 0;
+			alu_b <= 0;
+			alu_op <= 0;
+		end
+	end
+	
+	if(stage == 2'b00 || stage == 2'b01) begin
+		seg_buf_numbers[0] <= alu_a[7:4];
+		seg_buf_numbers[1] <= alu_a[3:0];
+		seg_buf_numbers[2] <= alu_b[7:4];
+		seg_buf_numbers[3] <= alu_b[3:0];
+	end else if(stage == 2'b10) begin
+		seg_buf_numbers[0] <= alu_op[7:4];
+		seg_buf_numbers[1] <= alu_op[3:0];
+		seg_buf_numbers[2] <= 0;
+		seg_buf_numbers[3] <= 0;
+	end else if(stage == 2'b11) begin
+		seg_buf_numbers[0] <= alu_out[7:4];
+		seg_buf_numbers[1] <= alu_out[3:0];
+		seg_buf_numbers[2] <= alu_flags[7:4];
+		seg_buf_numbers[3] <= alu_flags[3:0];
+	end
+	
+	select_out[0] <= ~debounce;
+	select_out[1] <= write;
+	select_out[2] <= next;
+	select_out[3] <= latch;
+end
+endmodule
diff --git a/VDivider.v b/VDivider.v
new file mode 100644
index 0000000..6f68b69
--- /dev/null
+++ b/VDivider.v
@@ -0,0 +1,27 @@
+module VDivider(
+	input wire clk,		// Clock input
+	input wire [divide_reg_size-1:0] compare_to,
+	output wire divided	// Divided output
+);
+
+// Parameters for division circuit
+parameter divide_reg_size;
+parameter pulsemode = 1;
+
+reg [divide_reg_size-1:0] div;	// Division counter
+reg div_int;							// Internal division result state
+
+assign divided = div_int;			// Assign internal result state to external output
+
+// Division
+always @ (posedge clk) begin
+	if(div >= compare_to) begin
+		div_int <= pulsemode ? 1 : ~div_int;
+		div <= 0;
+	end else begin
+		if(pulsemode) div_int <= 0;
+		div <= div + 1;
+	end
+end
+
+endmodule
diff --git a/altpll0.ppf b/altpll0.ppf
new file mode 100644
index 0000000..fbedb09
--- /dev/null
+++ b/altpll0.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="altpll0" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/altpll0.qip b/altpll0.qip
new file mode 100644
index 0000000..d7a9968
--- /dev/null
+++ b/altpll0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll0.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"]
diff --git a/altpll0.v b/altpll0.v
new file mode 100644
index 0000000..5781e93
--- /dev/null
+++ b/altpll0.v
@@ -0,0 +1,385 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: altpll0.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 12.0 Build 178 05/31/2012 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2012 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpll0 (
+	inclk0,
+	c0,
+	c1,
+	c2,
+	c3);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  c3;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [3:3] sub_wire2 = sub_wire0[3:3];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  c3 = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.inclk (sub_wire6),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "LOW",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 4,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 1,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 6,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.clk3_divide_by = 1,
+		altpll_component.clk3_duty_cycle = 50,
+		altpll_component.clk3_multiply_by = 8,
+		altpll_component.clk3_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpll0",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_USED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "200.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "400.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "6"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "8"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "6"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/altpll0_bb.v b/altpll0_bb.v
new file mode 100644
index 0000000..5b585ad
--- /dev/null
+++ b/altpll0_bb.v
@@ -0,0 +1,260 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: altpll0.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 12.0 Build 178 05/31/2012 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2012 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module altpll0 (
+	inclk0,
+	c0,
+	c1,
+	c2,
+	c3);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  c3;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "200.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "400.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "6"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "8"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "6"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON