diff --git a/ALU.v b/ALU.v
index 21c60e5..4f32fff 100644
--- a/ALU.v
+++ b/ALU.v
@@ -44,7 +44,7 @@ genvar i;
 generate
    for(i = 0; i<LOG2_BITS; i = i + 1) begin : shifters
       LeftBitShifter #(.bits(BITS), .shiftby(2**i)) lsh(i==0 ? a : lshift[i-1], b[i], shift_rotate, lshift[i], lshift_overflow[i]);
-		RightBitShifter #(.bits(BITS), .shiftby(2**i)) rsh(i==0 ? a : rshift[i-1], b[i], shift_rotate, rshift[i], rshift_underflow[i]);
+      RightBitShifter #(.bits(BITS), .shiftby(2**i)) rsh(i==0 ? a : rshift[i-1], b[i], shift_rotate, rshift[i], rshift_underflow[i]);
    end
 endgenerate
 
@@ -143,9 +143,9 @@ always @* begin
          i_z <= ~(a ^ b);
          i_flg <= 8'b0;
       end
-		
+      
       // CL_MUL
-		/*
+      /*
       12: begin
          i_z <=
             (a[7] ? b << 7 : 16'b0) ^
@@ -156,7 +156,7 @@ always @* begin
             (a[2] ? b << 2 : 16'b0) ^
             (a[1] ? b << 1 : 16'b0) ^
             (a[0] ? b      : 16'b0);
-			
+         
          i_flg <=
             (a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
             (a[6] && (b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
@@ -168,7 +168,7 @@ always @* begin
             ? 8'b1 : 8'b0;
       end
       */
-		
+      
       // SHR (flag: rotate)
       13: begin
          shift_rotate <= op[5];
@@ -225,8 +225,8 @@ endmodule
 
 module Combine(
     input wire  i1,
-	 input wire  i2,
-	 output wire o
+    input wire  i2,
+    output wire o
 );
 
 assign o = i1 | i2;
diff --git a/Callback.v b/Callback.v
index 8da2464..975e879 100644
--- a/Callback.v
+++ b/Callback.v
@@ -1,8 +1,8 @@
 module Callback(
-	input wire clk,
-	input wire [ISIZE-1:0] countdown,
-	input wire reset,
-	output wire callback
+   input wire clk,
+   input wire [ISIZE-1:0] countdown,
+   input wire reset,
+   output wire callback
 );
 
 parameter ISIZE;
@@ -13,12 +13,12 @@ reg [2:0] ctr_trigger = 2'b00;
 assign callback = !counter && ctr_trigger ? 1'b1 : 1'b0;
 
 always @(posedge clk or posedge reset) begin
-	if(reset) begin
-		counter <= countdown;
-		ctr_trigger <= 2'b10;
-	end
-	else if(counter) counter <= counter - 1'b1;
-	else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
+   if(reset) begin
+      counter <= countdown;
+      ctr_trigger <= 2'b10;
+   end
+   else if(counter) counter <= counter - 1'b1;
+   else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
 end
 
 endmodule
diff --git a/Divider.v b/Divider.v
index ee779ee..5afb452 100644
--- a/Divider.v
+++ b/Divider.v
@@ -1,6 +1,6 @@
 module Divider(
-	input wire clk,		// Clock input
-	output wire divided	// Divided output
+   input wire clk,      // Clock input
+   output wire divided   // Divided output
 );
 
 // Parameters for division circuit
@@ -8,20 +8,20 @@ parameter divideby = 1;
 parameter divide_reg_size;
 parameter pulsemode = 1;
 
-reg [divide_reg_size-1:0] div;	// Division counter
-reg div_int;							// Internal division result state
+reg [divide_reg_size-1:0] div;   // Division counter
+reg div_int;                     // Internal division result state
 
-assign divided = div_int;			// Assign internal result state to external output
+assign divided = div_int;         // Assign internal result state to external output
 
 // Division
 always @ (posedge clk) begin
-	if(div == divideby) begin
-		div_int <= pulsemode ? 1'b1 : ~div_int;
-		div <= 0;
-	end else begin
-		if(pulsemode) div_int <= 0;
-		div <= div + 1'b1;
-	end
+   if(div == divideby) begin
+      div_int <= pulsemode ? 1'b1 : ~div_int;
+      div <= 0;
+   end else begin
+      if(pulsemode) div_int <= 0;
+      div <= div + 1'b1;
+   end
 end
 
 endmodule
diff --git a/RAM.v b/RAM.v
index e8c55a4..13507e0 100644
--- a/RAM.v
+++ b/RAM.v
@@ -24,8 +24,8 @@ module RAM(
    input  wire [1:0]   access_bank,      // Which bank to access
    output wire         op_trigger,       // Event trigger wire
    input  wire [11:0]  address_select,   // Address selection when accessing RAM,
-	input  wire         stop_access,      // Close a row
-	output reg  [1:0]   op_bank           // Bank being accessed when op_trigger is pulled high
+   input  wire         stop_access,      // Close a row
+   output reg  [1:0]   op_bank           // Bank being accessed when op_trigger is pulled high
 );
 
 parameter CPB = 4;                       // Specifies in bit length how many cycles a bank burst can allocate for itself before other banks are checked
@@ -36,11 +36,11 @@ reg  [CPB-1:0] acc_cycles;               // Cycles used on current bank
 reg  [1:0]     acc_bank;                 // Which bank is allocating read cycles
 reg  [1:0]     acc_close[0:3];           // Requests a close of the current row
 reg  [3:0]     acc_type;                 // The current access type of the bank (0: READ, 1: WRITE)
-reg  [3:0]     acc_state [0:3];			  // Current access state for each bank (0: READY, 1: OPENING, 2: tRCD, 3: READ, 4: STOPPING)
+reg  [3:0]     acc_state [0:3];           // Current access state for each bank (0: READY, 1: OPENING, 2: tRCD, 3: READ, 4: STOPPING)
 reg  [3:0]     acc_init_callback;        // Pull this high to initiate a callback
 reg  [1:0]     event_trigger;            // Event triggers drive op_trigger
 
-wire [3:0]     acc_event;					  // Event update callback wire
+wire [3:0]     acc_event;                 // Event update callback wire
 wire [2:0]     callback_timeout[0:3];    // Callback clock cycle definition
 
 Callback #(.ISIZE(3)) cb0(clk, callback_timeout[0], acc_init_callback[0], acc_event[0]);
@@ -62,124 +62,124 @@ assign RAM_clk_enable = (acc_state[0] | acc_state[1] | acc_state[2] | acc_state[
 
 genvar n;
 generate
-	for(n = 0; n < 4; n = n + 1) begin : gen_callback_timing
-		assign callback_timeout[n] = acc_state[n][1] ? tRAS : tRCD;
-	end
+   for(n = 0; n < 4; n = n + 1) begin : gen_callback_timing
+      assign callback_timeout[n] = acc_state[n][1] ? tRAS : tRCD;
+   end
 endgenerate
 
 integer i;
 
 always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge stop_access or posedge clk) begin
-	if(read_rq || write_rq) begin
-		if(acc_state[access_bank] == 4'b0000) begin
-			RAM_enable <= 1'b0;
-			RAM_strobe_row <= 1'b0;
-			RAM_strobe_col <= 1'b1;
-			RAM_write_enable <= 1'b1;
-	
-			RAM_bank_sel <= access_bank;
-			RAM_addr <= {address_select[11], address_select[9:0]};
-			RAM_A10 <= address_select[10];
-			acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1;
-			acc_state[access_bank] <= 4'b0001;
-			acc_init_callback[access_bank] <= 1'b1;
-			acc_close[access_bank] <= 1'b0;
-		end
-	end
-	else if(stop_access) begin
-		if(acc_state[access_bank])
-			acc_close[access_bank] <= 1'b1;
-	end
-	else if(clk) begin
-		for(i = 0; i < 4; i = i + 1)
-			if(acc_state[i] == 4'b0010)
-				acc_init_callback[i] <= 1'b1;
-		
-		if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]))
-			RAM_enable <= 1'b1;
-		
-		// Bank access management
-		acc_cycles[acc_bank] <= acc_cycles[acc_bank] + 1'b1;
-		if(acc_cycles[acc_bank] == {CPB{1'b1}}) begin
-			
-			// Close banks as needed
-			if(acc_close[0]) begin
-				acc_close[0] <= 1'b0;
-				RAM_bank_sel <= 2'b00;
-				acc_state[0] <= 4'b0000;
-			end
-			else if(acc_close[1]) begin
-				acc_close[1] <= 1'b0;
-				RAM_bank_sel <= 2'b01;
-				acc_state[1] <= 4'b0000;
-			end
-			else if(acc_close[2]) begin
-				acc_close[2] <= 1'b0;
-				RAM_bank_sel <= 2'b10;
-				acc_state[2] <= 4'b0000;
-			end
-			else if(acc_close[3]) begin
-				acc_close[3] <= 1'b0;
-				RAM_bank_sel <= 2'b11;
-				acc_state[3] <= 4'b0000;
-			end
-			
-			// Increment bank tracker
-			if(~(acc_close[0] | acc_close[1] | acc_close[2] | acc_close[3])) begin
-				acc_bank <= acc_bank + 1;
-				acc_cycles <= {CPB{1'b0}};
-			end
-			else begin
-				// Trigger RAM row-close event
-				RAM_enable <= 1'b0;
-				RAM_strobe_row <= 1'b1;
-				RAM_strobe_col <= 1'b1;
-				RAM_write_enable <= 1'b0;
-			end
-		end
-		else begin
-			// Access bank
-			for(i = 0; i < 4; i = i + 1) begin
-				// Bank_{i} active and not closing and...
-				// Enough cycles left or when no other bank is active or...
-				// Bank_{i+1} at cycle limit and next banks inactive or bank is closing or...
-				// Bank_{i+2} at cycle limit and next bank inactive or bank is closing or...
-				// Bank_{i+3} at cycle limit or closing
-				if(!acc_close[i] && acc_state[i] == 4'b0100 && (                                                                                            
-					(acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 4'b0100 && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100))) ||
-					(acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100)) ||
-					(acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 4'b0100)) ||
-					(acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}}))
-				)) begin
-					RAM_bank_sel <= i;
-					RAM_addr <= {2'b0, RAM_addr[7:0]};
-					RAM_A10 <= 1'b1;
-					RAM_strobe_row <= 1'b1;
-					RAM_strobe_col <= 1'b0;
-					RAM_write_enable <= ~acc_type[i];
-					op_bank <= i;
-					event_trigger[0] <= event_trigger[1] ? 1'b0 : 1'b1;
-				end
-			end
-		end
-	end
-	else if(acc_event) begin
-		for(i = 0; i < 4; i = i + 1) begin
-			if(acc_state[i] == 4'b0001) begin
-				RAM_bank_sel <= i;
-				RAM_strobe_row <= 1'b1;
-				RAM_strobe_col <= 1'b0;
-				RAM_write_enable <= ~acc_type[i];
-				RAM_A10 <= 1;
-				acc_state[i] <= 4'b0010;
-				acc_init_callback[i] <= 1'b0;
-			end
-			else if(acc_state[i] == 4'b0010) begin
-				acc_init_callback[i] <= 1'b0;
-				acc_state[i] <= 4'b0100;
-			end
-		end
-	end
+   if(read_rq || write_rq) begin
+      if(acc_state[access_bank] == 4'b0000) begin
+         RAM_enable <= 1'b0;
+         RAM_strobe_row <= 1'b0;
+         RAM_strobe_col <= 1'b1;
+         RAM_write_enable <= 1'b1;
+   
+         RAM_bank_sel <= access_bank;
+         RAM_addr <= {address_select[11], address_select[9:0]};
+         RAM_A10 <= address_select[10];
+         acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1;
+         acc_state[access_bank] <= 4'b0001;
+         acc_init_callback[access_bank] <= 1'b1;
+         acc_close[access_bank] <= 1'b0;
+      end
+   end
+   else if(stop_access) begin
+      if(acc_state[access_bank])
+         acc_close[access_bank] <= 1'b1;
+   end
+   else if(clk) begin
+      for(i = 0; i < 4; i = i + 1)
+         if(acc_state[i] == 4'b0010)
+            acc_init_callback[i] <= 1'b1;
+      
+      if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]))
+         RAM_enable <= 1'b1;
+      
+      // Bank access management
+      acc_cycles[acc_bank] <= acc_cycles[acc_bank] + 1'b1;
+      if(acc_cycles[acc_bank] == {CPB{1'b1}}) begin
+         
+         // Close banks as needed
+         if(acc_close[0]) begin
+            acc_close[0] <= 1'b0;
+            RAM_bank_sel <= 2'b00;
+            acc_state[0] <= 4'b0000;
+         end
+         else if(acc_close[1]) begin
+            acc_close[1] <= 1'b0;
+            RAM_bank_sel <= 2'b01;
+            acc_state[1] <= 4'b0000;
+         end
+         else if(acc_close[2]) begin
+            acc_close[2] <= 1'b0;
+            RAM_bank_sel <= 2'b10;
+            acc_state[2] <= 4'b0000;
+         end
+         else if(acc_close[3]) begin
+            acc_close[3] <= 1'b0;
+            RAM_bank_sel <= 2'b11;
+            acc_state[3] <= 4'b0000;
+         end
+         
+         // Increment bank tracker
+         if(~(acc_close[0] | acc_close[1] | acc_close[2] | acc_close[3])) begin
+            acc_bank <= acc_bank + 1;
+            acc_cycles <= {CPB{1'b0}};
+         end
+         else begin
+            // Trigger RAM row-close event
+            RAM_enable <= 1'b0;
+            RAM_strobe_row <= 1'b1;
+            RAM_strobe_col <= 1'b1;
+            RAM_write_enable <= 1'b0;
+         end
+      end
+      else begin
+         // Access bank
+         for(i = 0; i < 4; i = i + 1) begin
+            // Bank_{i} active and not closing and...
+            // Enough cycles left or when no other bank is active or...
+            // Bank_{i+1} at cycle limit and next banks inactive or bank is closing or...
+            // Bank_{i+2} at cycle limit and next bank inactive or bank is closing or...
+            // Bank_{i+3} at cycle limit or closing
+            if(!acc_close[i] && acc_state[i] == 4'b0100 && (                                                                                            
+               (acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 4'b0100 && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100))) ||
+               (acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100)) ||
+               (acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 4'b0100)) ||
+               (acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}}))
+            )) begin
+               RAM_bank_sel <= i;
+               RAM_addr <= {2'b0, RAM_addr[7:0]};
+               RAM_A10 <= 1'b1;
+               RAM_strobe_row <= 1'b1;
+               RAM_strobe_col <= 1'b0;
+               RAM_write_enable <= ~acc_type[i];
+               op_bank <= i;
+               event_trigger[0] <= event_trigger[1] ? 1'b0 : 1'b1;
+            end
+         end
+      end
+   end
+   else if(acc_event) begin
+      for(i = 0; i < 4; i = i + 1) begin
+         if(acc_state[i] == 4'b0001) begin
+            RAM_bank_sel <= i;
+            RAM_strobe_row <= 1'b1;
+            RAM_strobe_col <= 1'b0;
+            RAM_write_enable <= ~acc_type[i];
+            RAM_A10 <= 1;
+            acc_state[i] <= 4'b0010;
+            acc_init_callback[i] <= 1'b0;
+         end
+         else if(acc_state[i] == 4'b0010) begin
+            acc_init_callback[i] <= 1'b0;
+            acc_state[i] <= 4'b0100;
+         end
+      end
+   end
 end
 
 // Reset op_trigger by tracking posedge-driven event_trigger
diff --git a/SegmentHexEncoder.v b/SegmentHexEncoder.v
index 31c4c4d..92c367b 100644
--- a/SegmentHexEncoder.v
+++ b/SegmentHexEncoder.v
@@ -1,24 +1,24 @@
 module SegmentHexEncoder(
-	input wire [3:0] number,	// Binary number
-	output reg [7:0] encoded	// Encoded hex output
+   input wire [3:0] number,   // Binary number
+   output reg [7:0] encoded   // Encoded hex output
 );
 always @*
-	case(number)
-		0: encoded <= 8'hC0;
-		1: encoded <= 8'hF9;
-		2: encoded <= 8'hA4;
-		3: encoded <= 8'hB0;
-		4: encoded <= 8'h99;
-		5: encoded <= 8'h92;
-		6: encoded <= 8'h82;
-		7: encoded <= 8'hF8;
-		8: encoded <= 8'h80;
-		9: encoded <= 8'h98;
-		10: encoded <= 8'h88;
-		11: encoded <= 8'h83;
-		12: encoded <= 8'hC6;
-		13: encoded <= 8'hA1;
-		14: encoded <= 8'h86;
-		default: encoded <= 8'h8E;
-	endcase
+   case(number)
+      0: encoded <= 8'hC0;
+      1: encoded <= 8'hF9;
+      2: encoded <= 8'hA4;
+      3: encoded <= 8'hB0;
+      4: encoded <= 8'h99;
+      5: encoded <= 8'h92;
+      6: encoded <= 8'h82;
+      7: encoded <= 8'hF8;
+      8: encoded <= 8'h80;
+      9: encoded <= 8'h98;
+      10: encoded <= 8'h88;
+      11: encoded <= 8'h83;
+      12: encoded <= 8'hC6;
+      13: encoded <= 8'hA1;
+      14: encoded <= 8'h86;
+      default: encoded <= 8'h8E;
+   endcase
 endmodule
diff --git a/SegmentManager.v b/SegmentManager.v
index b790ebe..dd4db23 100644
--- a/SegmentManager.v
+++ b/SegmentManager.v
@@ -1,34 +1,34 @@
 module SegmentManager(
-	input wire clk,						// 50MHz clock signal
-	input wire [7:0] segment_data0,	// Segment data for segment 0 (D1)
-	input wire [7:0] segment_data1,	// Segment data for segment 1 (D2)
-	input wire [7:0] segment_data2,	// Segment data for segment 2 (D3)
-	input wire [7:0] segment_data3,	// Segment data for segment 3 (D4)
-	output reg [3:0] segment_select,	// 7-segment display selector
-	output reg [7:0] segments			// Segment display bus
+   input wire clk,                   // 50MHz clock signal
+   input wire [7:0] segment_data0,   // Segment data for segment 0 (D1)
+   input wire [7:0] segment_data1,   // Segment data for segment 1 (D2)
+   input wire [7:0] segment_data2,   // Segment data for segment 2 (D3)
+   input wire [7:0] segment_data3,   // Segment data for segment 3 (D4)
+   output reg [3:0] segment_select,  // 7-segment display selector
+   output reg [7:0] segments         // Segment display bus
 );
 
 initial segment_select = 4'b1110;
 
-reg [1:0] seg_sel_track;	// Active display tracker
+reg [1:0] seg_sel_track;   // Active display tracker
 
-wire clk_graphics;			// Internal clock divider output
+wire clk_graphics;         // Internal clock divider output
 
 // Clock division circuit
-Divider #(.divideby(25000), .divide_reg_size(17)) divider_audio(clk, clk_graphics);	// Frequency: 50MHz/25k = 2kHz	TriggerType: Pulse
+Divider #(.divideby(25000), .divide_reg_size(17)) divider_audio(clk, clk_graphics);   // Frequency: 50MHz/25k = 2kHz   TriggerType: Pulse
 
 // Change the active segment data
 always @(posedge clk_graphics) begin
-	segment_select <=(segment_select << 1) | segment_select[3];
-	seg_sel_track <= seg_sel_track + 1'b1;
+   segment_select <=(segment_select << 1) | segment_select[3];
+   seg_sel_track <= seg_sel_track + 1'b1;
 end
 
 // Assign the active segment data to the segment bus
 always @*
-	case(seg_sel_track)
-		0: 		segments <= segment_data0;
-		1: 		segments <= segment_data1;
-		2: 		segments <= segment_data2;
-		default: segments <= segment_data3;
-	endcase
+   case(seg_sel_track)
+      0:       segments <= segment_data0;
+      1:       segments <= segment_data1;
+      2:       segments <= segment_data2;
+      default: segments <= segment_data3;
+   endcase
 endmodule
diff --git a/SevenSegment.v b/SevenSegment.v
index c65bc0d..07407e4 100644
--- a/SevenSegment.v
+++ b/SevenSegment.v
@@ -1,26 +1,26 @@
 module SevenSegment(
-	input wire         latch,            // S4
-	input wire         next,             // S2
-	input wire         value,            // S3
-	output reg  [3:0]  select_out,       // LED1-LED4 [0-3]
-	input wire         write,            // S1
-	input wire         clk,              // 50MHz clock
-	output      [3:0]  seg_select,       // Q1-Q4      [0-3]
-	output      [7:0]  seg_write,        // a-g + dp   [0-7] + 8
-	output reg         beep,             // Buzzer
-	output wire [10:0] RAM_addr,         // RAM address buffer
-	output wire        RAM_A10,          // RAM A10 precharge/address
-	output wire [1:0]  RAM_bank_sel,     // RAM bank selection
-	inout  wire [15:0] RAM_data,         // RAM data bus
-	output wire        RAM_clk,          // RAM clock signal
-	output wire        RAM_clk_enable,   // RAM enable clock
-	output wire        RAM_enable,       // RAM chip enable
-	output wire        RAM_strobe_row,   // RAM row strobe
-	output wire        RAM_strobe_col,   // RAM column strobe
-	output wire        RAM_write_enable, // RAM data bus write enable
-	output wire        VGA_vsync,        // VGA display vsync trigger
-	output wire        VGA_hsync,        // VGA display hsync trigger
-	output wire [2:0]  VGA_rgb           // VGA color channels [0]: RED, [1]: GREEN, [2]: BLUE
+   input wire         latch,            // S4
+   input wire         next,             // S2
+   input wire         value,            // S3
+   output reg  [3:0]  select_out,       // LED1-LED4 [0-3]
+   input wire         write,            // S1
+   input wire         clk,              // 50MHz clock
+   output      [3:0]  seg_select,       // Q1-Q4      [0-3]
+   output      [7:0]  seg_write,        // a-g + dp   [0-7] + 8
+   output reg         beep,             // Buzzer
+   output wire [10:0] RAM_addr,         // RAM address buffer
+   output wire        RAM_A10,          // RAM A10 precharge/address
+   output wire [1:0]  RAM_bank_sel,     // RAM bank selection
+   inout  wire [15:0] RAM_data,         // RAM data bus
+   output wire        RAM_clk,          // RAM clock signal
+   output wire        RAM_clk_enable,   // RAM enable clock
+   output wire        RAM_enable,       // RAM chip enable
+   output wire        RAM_strobe_row,   // RAM row strobe
+   output wire        RAM_strobe_col,   // RAM column strobe
+   output wire        RAM_write_enable, // RAM data bus write enable
+   output wire        VGA_vsync,        // VGA display vsync trigger
+   output wire        VGA_hsync,        // VGA display hsync trigger
+   output wire [2:0]  VGA_rgb           // VGA color channels [0]: RED, [1]: GREEN, [2]: BLUE
 );
 
 // ----    SETTINGS    ---- //
@@ -69,13 +69,13 @@ SegmentHexEncoder enc3(.number (seg_buf_numbers[3]), .encoded (seg_buf[3]));
 
 // A segment display manager to handle rendering data to the 7-segment displays
 SegmentManager seg_display(
-	.clk (clk), 
-	.segment_data0 (seg_buf[0]),
-	.segment_data1 (seg_buf[1]),
-	.segment_data2 (seg_buf[2]),
-	.segment_data3 (seg_buf[3]),
-	.segment_select (seg_select),
-	.segments (seg_write)
+   .clk (clk), 
+   .segment_data0 (seg_buf[0]),
+   .segment_data1 (seg_buf[1]),
+   .segment_data2 (seg_buf[2]),
+   .segment_data3 (seg_buf[3]),
+   .segment_select (seg_select),
+   .segments (seg_write)
 );
 
 // Graphics controller
@@ -92,94 +92,94 @@ Callback #(.ISIZE(32)) timeout(pll[0], 32'd100000000, ~value, cb);
 
 // RAM module
 RAM main_memory(
-	pll[RAM_PLL],
-	RAM_addr,
-	RAM_A10,
-	RAM_bank_sel,
-	RAM_data,
-	RAM_clk,
-	RAM_clk_enable,
-	RAM_enable,
-	RAM_strobe_col,
-	RAM_strobe_row,
-	RAM_write_enable,
-	ram_request_read,
-	ram_request_write,
-	ram_bank_sel,
-	ram_event,
-	ram_addr,
-	ram_close,
-	ram_event_bank
+   pll[RAM_PLL],
+   RAM_addr,
+   RAM_A10,
+   RAM_bank_sel,
+   RAM_data,
+   RAM_clk,
+   RAM_clk_enable,
+   RAM_enable,
+   RAM_strobe_col,
+   RAM_strobe_row,
+   RAM_write_enable,
+   ram_request_read,
+   ram_request_write,
+   ram_bank_sel,
+   ram_event,
+   ram_addr,
+   ram_close,
+   ram_event_bank
 );
 
 always @(posedge cb or negedge value) select_out <= cb ? 4'b0000 : 4'b1111;
 always @(posedge vga_clk) gfx_rgb <= alu_a[2:0];
 always @(posedge pll[PLL_SELECT]) begin
-	if(!latch && write && next) begin
-		debounce <= 1'b1;
-	end
-	
-	if(write && next && db_trap) begin
-		debounce <= 1'b0;
-		db_trap <= 1'b0;
-	end
-	
-	if(!write && debounce && !db_trap) begin
-		db_trap <= 1'b1;
-		if(stage == 2'b0) begin
-			alu_a <= alu_a + 8'b1;
-		end else if(stage == 2'b1) begin
-			alu_b <= alu_b + 8'b1;
-		end else if(stage == 2'b10) begin
-			alu_op <= alu_op + 8'b1;
-		end
-	end else if (!next && debounce && !db_trap) begin
-		db_trap <= 1'b1;
-		stage <= stage + 2'b1;
-		
-		if(stage == 2'b01) begin
-			seg_buf_numbers[0] <= 4'b0;
-			seg_buf_numbers[1] <= 4'b0;
-			seg_buf_numbers[2] <= 4'b0;
-			seg_buf_numbers[3] <= 4'b0;
-		end
-		else if(stage == 2'b10) begin
-			seg_buf_numbers[0] <= alu_out[7:4];
-			seg_buf_numbers[1] <= alu_out[3:0];
-			seg_buf_numbers[2] <= alu_flags[7:4];
-			seg_buf_numbers[3] <= alu_flags[3:0];
-		end
-		else if(stage == 2'b11) begin
-			seg_buf_numbers[0] <= 4'b0;
-			seg_buf_numbers[1] <= 4'b0;
-			seg_buf_numbers[2] <= 4'b0;
-			seg_buf_numbers[3] <= 4'b0;
-			alu_a <= 8'b0;
-			alu_b <= 8'b0;
-			alu_op <= 8'b0;
-		end
-	end
-	
-	if(stage == 2'b00 || stage == 2'b01) begin
-		seg_buf_numbers[0] <= alu_a[7:4];
-		seg_buf_numbers[1] <= alu_a[3:0];
-		seg_buf_numbers[2] <= alu_b[7:4];
-		seg_buf_numbers[3] <= alu_b[3:0];
-	end else if(stage == 2'b10) begin
-		seg_buf_numbers[0] <= alu_op[7:4];
-		seg_buf_numbers[1] <= alu_op[3:0];
-		seg_buf_numbers[2] <= 4'b0;
-		seg_buf_numbers[3] <= 4'b0;
-	end else if(stage == 2'b11) begin
-		seg_buf_numbers[0] <= alu_out[7:4];
-		seg_buf_numbers[1] <= alu_out[3:0];
-		seg_buf_numbers[2] <= alu_flags[7:4];
-		seg_buf_numbers[3] <= alu_flags[3:0];
-	end
-	
-	//select_out[0] <= ~debounce;
-	//select_out[1] <= write;
-	//select_out[2] <= next;
-	//select_out[3] <= latch;
+   if(!latch && write && next) begin
+      debounce <= 1'b1;
+   end
+   
+   if(write && next && db_trap) begin
+      debounce <= 1'b0;
+      db_trap <= 1'b0;
+   end
+   
+   if(!write && debounce && !db_trap) begin
+      db_trap <= 1'b1;
+      if(stage == 2'b0) begin
+         alu_a <= alu_a + 8'b1;
+      end else if(stage == 2'b1) begin
+         alu_b <= alu_b + 8'b1;
+      end else if(stage == 2'b10) begin
+         alu_op <= alu_op + 8'b1;
+      end
+   end else if (!next && debounce && !db_trap) begin
+      db_trap <= 1'b1;
+      stage <= stage + 2'b1;
+      
+      if(stage == 2'b01) begin
+         seg_buf_numbers[0] <= 4'b0;
+         seg_buf_numbers[1] <= 4'b0;
+         seg_buf_numbers[2] <= 4'b0;
+         seg_buf_numbers[3] <= 4'b0;
+      end
+      else if(stage == 2'b10) begin
+         seg_buf_numbers[0] <= alu_out[7:4];
+         seg_buf_numbers[1] <= alu_out[3:0];
+         seg_buf_numbers[2] <= alu_flags[7:4];
+         seg_buf_numbers[3] <= alu_flags[3:0];
+      end
+      else if(stage == 2'b11) begin
+         seg_buf_numbers[0] <= 4'b0;
+         seg_buf_numbers[1] <= 4'b0;
+         seg_buf_numbers[2] <= 4'b0;
+         seg_buf_numbers[3] <= 4'b0;
+         alu_a <= 8'b0;
+         alu_b <= 8'b0;
+         alu_op <= 8'b0;
+      end
+   end
+   
+   if(stage == 2'b00 || stage == 2'b01) begin
+      seg_buf_numbers[0] <= alu_a[7:4];
+      seg_buf_numbers[1] <= alu_a[3:0];
+      seg_buf_numbers[2] <= alu_b[7:4];
+      seg_buf_numbers[3] <= alu_b[3:0];
+   end else if(stage == 2'b10) begin
+      seg_buf_numbers[0] <= alu_op[7:4];
+      seg_buf_numbers[1] <= alu_op[3:0];
+      seg_buf_numbers[2] <= 4'b0;
+      seg_buf_numbers[3] <= 4'b0;
+   end else if(stage == 2'b11) begin
+      seg_buf_numbers[0] <= alu_out[7:4];
+      seg_buf_numbers[1] <= alu_out[3:0];
+      seg_buf_numbers[2] <= alu_flags[7:4];
+      seg_buf_numbers[3] <= alu_flags[3:0];
+   end
+   
+   //select_out[0] <= ~debounce;
+   //select_out[1] <= write;
+   //select_out[2] <= next;
+   //select_out[3] <= latch;
 end
 endmodule
diff --git a/VDivider.v b/VDivider.v
index 6f68b69..5234484 100644
--- a/VDivider.v
+++ b/VDivider.v
@@ -1,27 +1,27 @@
 module VDivider(
-	input wire clk,		// Clock input
-	input wire [divide_reg_size-1:0] compare_to,
-	output wire divided	// Divided output
+   input wire clk,       // Clock input
+   input wire [divide_reg_size-1:0] compare_to,
+   output wire divided   // Divided output
 );
 
 // Parameters for division circuit
 parameter divide_reg_size;
 parameter pulsemode = 1;
 
-reg [divide_reg_size-1:0] div;	// Division counter
-reg div_int;							// Internal division result state
+reg [divide_reg_size-1:0] div;   // Division counter
+reg div_int;                     // Internal division result state
 
-assign divided = div_int;			// Assign internal result state to external output
+assign divided = div_int;         // Assign internal result state to external output
 
 // Division
 always @ (posedge clk) begin
-	if(div >= compare_to) begin
-		div_int <= pulsemode ? 1 : ~div_int;
-		div <= 0;
-	end else begin
-		if(pulsemode) div_int <= 0;
-		div <= div + 1;
-	end
+   if(div >= compare_to) begin
+      div_int <= pulsemode ? 1 : ~div_int;
+      div <= 0;
+   end else begin
+      if(pulsemode) div_int <= 0;
+      div <= div + 1;
+   end
 end
 
 endmodule
diff --git a/VGA.v b/VGA.v
index ed1c8dc..000c7f4 100644
--- a/VGA.v
+++ b/VGA.v
@@ -1,12 +1,12 @@
 module VGA(
-	input  wire       clk,
-	input wire [2:0]  rgb_data,
-	output reg        graphics_clk,
-	output wire [9:0] graphics_coords_x,
-	output wire [9:0] graphics_coords_y,
-	output wire [2:0] VGA_rgb,
-	output wire       VGA_hsync,
-	output wire       VGA_vsync
+   input  wire       clk,
+   input wire [2:0]  rgb_data,
+   output reg        graphics_clk,
+   output wire [9:0] graphics_coords_x,
+   output wire [9:0] graphics_coords_y,
+   output wire [2:0] VGA_rgb,
+   output wire       VGA_hsync,
+   output wire       VGA_vsync
 );
 
 parameter