From e7f9e007d99ea9dd99e76397d8817679d0ee9a0d Mon Sep 17 00:00:00 2001 From: GabrielTofvesson Date: Thu, 18 Oct 2018 03:08:06 +0200 Subject: [PATCH] Added cache module Update VGA module Quadrupled pixel clock Doubled resolution to 1280x800 Added ZigZag encode/decode to ALU --- .gitignore | 3 +- ALU.v | 12 +++- SevenSegment.v | 56 +++++++++++++++- VGA.v | 50 ++++++++------ cache.qip | 4 ++ cache.v | 174 +++++++++++++++++++++++++++++++++++++++++++++++++ cache_bb.v | 124 +++++++++++++++++++++++++++++++++++ 7 files changed, 397 insertions(+), 26 deletions(-) create mode 100644 cache.qip create mode 100644 cache.v create mode 100644 cache_bb.v diff --git a/.gitignore b/.gitignore index 247302c..650a15e 100644 --- a/.gitignore +++ b/.gitignore @@ -24,4 +24,5 @@ incremental_db/* *.qws *.qsf *.qpf -.sopc_builder/* \ No newline at end of file +.sopc_builder/* +.qsys_edit/* \ No newline at end of file diff --git a/ALU.v b/ALU.v index 4f32fff..ab8a0c8 100644 --- a/ALU.v +++ b/ALU.v @@ -94,7 +94,7 @@ always @* begin 101 -> a >= b 110 -> a <= b 111 -> No output - + */ i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 16'b0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 16'b1 : 16'b0; i_flg <= @@ -168,7 +168,15 @@ always @* begin ? 8'b1 : 8'b0; end */ - + + // ZZ_ED (flag: decode) + 12: begin + i_z <= op[7] ? + {a[0], a[BITS-1:1] ^ (a[0] ? {(BITS-1){1'b1}} : 1'b0)} : // Decode + {a[BITS-2:0] ^ (a[BITS-1] ? {(BITS-1){1'b1}} : 1'b0), a[BITS-1]}; // Encode + i_flg <= 8'b0; + end + // SHR (flag: rotate) 13: begin shift_rotate <= op[5]; diff --git a/SevenSegment.v b/SevenSegment.v index 07407e4..f7494d0 100644 --- a/SevenSegment.v +++ b/SevenSegment.v @@ -24,7 +24,7 @@ module SevenSegment( ); // ---- SETTINGS ---- // -localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz +localparam PLL_SELECT = 3; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!! // ---- REGISTERS ---- // @@ -39,6 +39,10 @@ reg [2:0] gfx_rgb; // VGA color channels reg [1:0] ram_bank_sel; // Which ram bank to access reg [11:0] ram_addr; // RAM address selection reg ram_close; // RAM close-row trigger +reg [7:0] cache0_addr; // Cache0 access address +reg [15:0] cache0_data = 16'b0; // Data to write to cache0 +reg cache0_write; // Write-enable for cache0 + // ---- WIRES ---- // wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer) @@ -47,11 +51,16 @@ wire [7:0] alu_flags; // ALU (core0) output flags wire [4:0] pll; // Phase-locked-loop connections (+ source clock) wire vga_clk; // VGA data clock wire cb; // Callback/timeout -wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to +wire [11:0] vga_coords[0:1]; // Current screen coordinates being drawn to wire ram_request_read; // Trigger a read operation from main memory wire ram_request_write; // Trigger a write operation from main memory wire ram_event; // Event trigger from ram when a r/w operation is ready wire [1:0] ram_event_bank; // Which bank an event is happening on +wire [15:0] cache0_dq; // Data out from cache0 +wire i_latch = ~latch; // Latch input wire +wire i_value = ~value; // Value input wire +wire i_next = ~next; // Next input wire +wire i_write = ~write; // Write input wire // ---- WIRE ASSIGNS ---- // assign pll[4] = clk; @@ -78,8 +87,11 @@ SegmentManager seg_display( .segments (seg_write) ); +// 4096-bit internal cache memory +//cache c0(cache0_addr, pll[PLL_SELECT], cache0_data, cache0_write, cache0_dq); + // Graphics controller -VGA screen(clk, gfx_rgb, vga_clk, vga_coords[0], vga_coords[1], VGA_rgb, VGA_hsync, VGA_vsync); +VGA screen(pll[0], gfx_rgb, vga_clk, vga_coords[0], vga_coords[1], VGA_rgb, VGA_hsync, VGA_vsync); // Arithmetic logic unit ALU #(.BITS(8), .LOG2_BITS(3)) core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags)); @@ -112,6 +124,43 @@ RAM main_memory( ram_event_bank ); +// 1280x800 screen +always @(posedge pll[3]) begin + gfx_rgb <= vga_coords[0] == 0 || vga_coords[0] == 1278 || vga_coords[1] == 0 || vga_coords[1] == 799 ? 3'b111 : 3'b0; // Draw border along edge of screen +end + +always @(posedge i_latch or posedge i_write or posedge i_value or posedge i_next or posedge pll[PLL_SELECT]) begin + if(i_latch) debounce <= 1'b1; + else if(i_write) begin + debounce <= 1'b0; + if(debounce) begin + if(cache0_write) cache0_data <= cache0_data + 1'b1; + else cache0_write <= 1'b1; + end + end + else if(i_value) begin + debounce <= 1'b0; + if(debounce) begin + if(!cache0_write) cache0_addr <= cache0_addr + 1'b1; + else cache0_write <= 1'b0; + end + end + else if(i_next) begin + debounce <= 1'b0; + if(debounce) begin + if(!cache0_write) cache0_addr <= cache0_addr - 1'b1; + else cache0_write <= 1'b0; + end + end + else if(pll[PLL_SELECT]) begin + seg_buf_numbers[3] <= cache0_dq[3:0]; + seg_buf_numbers[2] <= cache0_dq[7:4]; + seg_buf_numbers[1] <= cache0_dq[11:8]; + seg_buf_numbers[0] <= cache0_dq[15:12]; + select_out <= {debounce ? 1'b0 : 1'b1, cache0_write ? 1'b0 : 1'b1, 2'b11}; + end +end +/* always @(posedge cb or negedge value) select_out <= cb ? 4'b0000 : 4'b1111; always @(posedge vga_clk) gfx_rgb <= alu_a[2:0]; always @(posedge pll[PLL_SELECT]) begin @@ -182,4 +231,5 @@ always @(posedge pll[PLL_SELECT]) begin //select_out[2] <= next; //select_out[3] <= latch; end +*/ endmodule diff --git a/VGA.v b/VGA.v index 000c7f4..2e89bdb 100644 --- a/VGA.v +++ b/VGA.v @@ -1,26 +1,35 @@ module VGA( input wire clk, input wire [2:0] rgb_data, - output reg graphics_clk, - output wire [9:0] graphics_coords_x, - output wire [9:0] graphics_coords_y, + output wire graphics_trigger, + output wire [11:0] graphics_coords_x, + output wire [11:0] graphics_coords_y, output wire [2:0] VGA_rgb, output wire VGA_hsync, output wire VGA_vsync ); parameter - hsync_end = 10'd95, - hdat_begin = 10'd143, - hdat_end = 10'd783, - hpixel_end = 10'd799, - vsync_end = 10'd1, - vdat_begin = 10'd34, - vdat_end = 10'd514, - vline_end = 10'd524; + //hsync_end = 10'd95, + //hdat_begin = 10'd143, + //hdat_end = 10'd783, + //hpixel_end = 10'd799, + //vsync_end = 10'd1, + //vdat_begin = 10'd34, + //vdat_end = 10'd514, + //vline_end = 10'd524; + hsync_end = 11'd190, + hdat_begin = 11'd286, + hdat_end = 11'd1566, + hpixel_end = 11'd1598, + vsync_end = 11'd1, + vdat_begin = 11'd68, + vdat_end = 11'd1028, + vline_end = 11'd1048; -reg [9:0] hcount; -reg [9:0] vcount; +reg [11:0] hcount; +reg [11:0] vcount; +wire graphics_clk = clk; wire hcount_ov = (hcount == hpixel_end); wire vcount_ov = (vcount == vline_end); @@ -29,17 +38,18 @@ wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vd assign VGA_hsync = (hcount > hsync_end); assign VGA_vsync = (vcount > vsync_end); assign VGA_rgb = (dat_act) ? rgb_data : 3'b0; -assign graphics_coords_x = vcount; -assign graphics_coords_y = hcount; +assign graphics_coords_x = hcount - hdat_begin; +assign graphics_coords_y = vcount - vdat_begin; +assign graphics_trigger = dat_act & graphics_clk; // Clock divider -always @(posedge clk) graphics_clk = ~graphics_clk; +//always @(posedge clk) graphics_clk = ~graphics_clk; // Graphics boundary calculation always @(posedge graphics_clk) begin - if(hcount_ov && vcount_ov) vcount <= 10'b0; - else if(hcount_ov) vcount <= vcount + 10'b1; - if (hcount_ov) hcount <= 10'd0; - else hcount <= hcount + 10'd1; + if(hcount_ov && vcount_ov) vcount <= 11'b0; + else if(hcount_ov) vcount <= vcount + 11'b1; + if (hcount_ov) hcount <= 11'd0; + else hcount <= hcount + 11'd1; end endmodule diff --git a/cache.qip b/cache.qip new file mode 100644 index 0000000..b4e4ffb --- /dev/null +++ b/cache.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "12.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cache.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cache_bb.v"] diff --git a/cache.v b/cache.v new file mode 100644 index 0000000..6c22d2c --- /dev/null +++ b/cache.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cache.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 12.0 Build 178 05/31/2012 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2012 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cache ( + address, + clock, + data, + wren, + q); + + input [7:0] address; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.width_a = 16, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/cache_bb.v b/cache_bb.v new file mode 100644 index 0000000..4be5fbb --- /dev/null +++ b/cache_bb.v @@ -0,0 +1,124 @@ +// megafunction wizard: %RAM: 1-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cache.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 12.0 Build 178 05/31/2012 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2012 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module cache ( + address, + clock, + data, + wren, + q); + + input [7:0] address; + input clock; + input [15:0] data; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" +// Retrieval info: PRIVATE: WidthData NUMERIC "16" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cache_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf