Add clickable links to README
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Gabriel Tofvesson
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README.md
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README.md
@ -7,7 +7,7 @@ microprogramming the LMIA system.
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## μASM instruction set
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### NOP
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No-operation. This wastes one clock cycle
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No-operation. This wastes one clock cycle.
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### MOV [regA] \[regB\]
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@ -15,11 +15,13 @@ Move value in *regA* to *regB*
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*This operation uses the bus*
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*If regB is LC, no other LC operation can be specified in the same cycle*
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*If regB is [LC](#lc), no other [LC](#lc) operation can be specified in the
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same cycle*
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### MVN {[reg] | [const]}
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Move the inverse of a value (from register or constant) into register [**AR**](#ar).
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Move the inverse of a value (from register or constant) into register
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[**AR**](#ar).
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*This operation uses the bus*
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@ -29,7 +31,7 @@ Move the inverse of a value (from register or constant) into register [**AR**](#
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### MVZ
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Set [**AR**](#ar) to zero.
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*Sets flags: Z, N*
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*Sets flags: [Z](#z), [N](#n)*
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### ADD {[reg] | [const]}
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@ -39,17 +41,17 @@ Add value (from register or constant) to register [**AR**](#ar).
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, O, C*
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*Sets flags: [Z](#z), [N](#n), [O](#o), [C](#c)*
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### SUB {[reg] | [const]}
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Subtract value (from register or constant) from register [**AR**](#ar) (see [*Registers*](#registers)).
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Subtract value (from register or constant) from register [**AR**](#ar).
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, O, C*
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*Sets flags: [Z](#z), [N](#n), [O](#o), [C](#c)*
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### AND {[reg] | [const]}
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@ -61,7 +63,7 @@ expect it to be removed in future releases.
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N*
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*Sets flags: [Z](#z), [N](#n)*
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### ORR {[reg] | [const]}
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@ -72,13 +74,13 @@ Perform bitwise Or with given value (from register or constant) and register
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N*
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*Sets flags: [Z](#z), [N](#n)*
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### ADN {[reg] | [const]}
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Add value (from register or constant) to register [**AR**](#ar) without updating
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flags.
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Add value (from register or constant) to register [**AR**](#ar) without
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updating flags.
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*This operation uses the bus*
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@ -92,18 +94,19 @@ Performs a logical shift left of [**AR**](#ar).
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### ISL
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Performs a logical shift left of [**AR**](#ar) and [**HR**](#hr) as if they were one 32-bit
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register where [**AR**](#ar) corresponds to the most-significant bits.
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Performs a logical shift left of [**AR**](#ar) and [**HR**](#hr) as if they
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were one 32-bit register where [**AR**](#ar) corresponds to the
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most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### ASR
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@ -113,18 +116,19 @@ Performs an arithmetic shift right on [**AR**](#ar).
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### ISR
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Performs an arithmetic shift right of [**AR**](#ar) and [**HR**](#hr) as if they were one
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32-bit register where [**AR**](#ar) corresponds to the most-significant bits.
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Performs an arithmetic shift right of [**AR**](#ar) and [**HR**](#hr) as if
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they were one 32-bit register where [**AR**](#ar) corresponds to the
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most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### LSR
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@ -134,7 +138,7 @@ Performs a logical shift right of [**AR**](#ar).
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### ROL
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@ -144,22 +148,23 @@ Performs an arithmetic rotate right on [**AR**](#ar).
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### IRL
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Performs an arithmetic shift left of [**AR**](#ar) and [**HR**](#hr) as if they were one
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32-bit register where [**AR**](#ar) corresponds to the most-significant bits.
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Performs an arithmetic shift left of [**AR**](#ar) and [**HR**](#hr) as if they
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were one 32-bit register where [**AR**](#ar) corresponds to the
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most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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*Sets flags: [Z](#z), [N](#n), [C](#c)*
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### LCSET [const]
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Set **LC** to value of constant.
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Set [**LC**](#lc) to value of constant.
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### CONST [const]
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@ -169,24 +174,24 @@ Set [**AR**](#ar) to value of cosntant.
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### INCPC
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Increment value in **PC** by one.
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Increment value in [**PC**](#pc) by one.
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### DECLC
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Decrement value in **LC** by one.
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Decrement value in [**LC**](#lc) by one.
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### CALL [label]
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Move value in **uPC** to **uSP** (**MySPC**) and set value in **uPC** to point
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Move value in [**uPC**](#upc) to [**uSP**](#usp) and set value in [**uPC**](#upc) to point
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to the address of the given label.
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### RET
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Move value in **uSP** (**MySPC**) into **uPC**.
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Move value in [**uSP**](#usp) into [**uPC**](#upc).
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### HALT
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Stop execution and set value in **uPC** to 0.
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Stop execution and set value in [**uPC**](#upc) to 0.
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### BRA [label]
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@ -227,16 +232,16 @@ Branch to address of label if [**O-flag**](#o) is 0.
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### BOP
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Branch to address specified by entry in optable pointed to by highest 4 bits
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in IR.
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in [**IR**](#ir).
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### BAM
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Branch to address specified by entry in addressing mode pointed to by M-bits in
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IR.
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[**IR**](#ir).
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### BST
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Branch to start. This sets value in **uPC** to 0.
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Branch to start. This sets value in [**uPC**](#upc) to 0.
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### RESET [reg]
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@ -263,10 +268,10 @@ Define an initial value in the program memory at the given address.
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Define a compile-time label at the given position in the microprogram. Labels
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can be referenced using an '@' symbol.
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For example: *$BAR* would declare a label *BAR* which can be referenced with
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*@BAR*.
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For example: `$BAR` would declare a label *BAR* which can be referenced with
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`@BAR`.
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**NOTE**: Label names are case-insensitive; i.e. @*FOO* and @*foo* are
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**NOTE**: Label names are case-insensitive; i.e. `@FOO` and `@foo` are
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functionally indistinguishable to the compiler.
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@ -287,23 +292,25 @@ greater than 127.
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## Flags
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Flags - *aside from L* - are set based on ALU operations, so they depend on
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**AR** and the **BUS**. Henceforth, unless otherwise implied or stated, [**AR**](#ar)
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will refer to the state/value of [**AR**](#ar) *after* an ALU operation.
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Flags - *aside from [L](#l)* - are set based on ALU operations, so they depend
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on [**AR*](#ar)* and the **BUS**. Henceforth, unless otherwise implied or
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stated, [**AR**](#ar) will refer to the state/value of [**AR**](#ar) *after* an
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ALU operation. Flags retain their state until an instruction which is declared
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as modifying said flag is executed.
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### Z
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Set if [**AR**](#ar) == **0**
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Set if [**AR**](#ar) == **0**.
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### N
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Set if sign bit in [**AR**](#ar) is set.
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### O
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Set if sign of [**AR**](#ar) differs from signs of both [**AR**](#ar) and **BUS** *before*
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the arithmetic operation.
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Set if sign of [**AR**](#ar) differs from signs of both [**AR**](#ar) *before*
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the arithmetic operation and of the **BUS**.
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### C
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Set if [**AR**](#ar) is less than or equal to [**AR**](#ar) *before* the arithmetic
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operation.
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Set if [**AR**](#ar) is less than or equal to [**AR**](#ar) *before* the
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arithmetic operation.
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### L
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Set if [**LC**](#lc) == 0.
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@ -341,17 +348,19 @@ can also be used to address a specific general register via the GR multiplexer
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### GR
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This is a shorthand for accessing the general register currently made available
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by the GR multiplexer when said MUX is controlled by the GRx bits in **IR**.
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by the GR multiplexer when said MUX is controlled by the GRx bits in
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[**IR**](#ir).
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**NOTE**: Only one GR can be accessed per cycle. Which register this is (of
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the four available registers) is determined by the value in **IR**.
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the four available registers) is determined by the value in [**IR**](#ir).
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### GRM
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This is a shorthand for accessing the general register currently made available
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by the GR multiplexer when said MUX is controlled by the M bits in **IR**.
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by the GR multiplexer when said MUX is controlled by the M bits in
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[**IR**](#ir).
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**NOTE**: Only one GR can be accessed per cycle. Which register this is (of
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the four available registers) is determined by the value in **IR**.
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the four available registers) is determined by the value in [**IR**](#ir).
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### LC
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The loopcounter register is a special register that can only be modified in
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@ -369,6 +378,37 @@ action to take for the register. The three ways of modifying it are as follows:
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value in LC can, though, to some degree be inferred from the [**L-flag**](#l)
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(see [*Flags*](#flags)).
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### PC
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The program counter. This register is only 8 bits wide. Writing a value larger
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than 8 bits to this register will simply truncate the binary string to 8 bits.
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Attemping to read a value from PC to a register of a larger width will result
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in the value in PC populating the lowesr 8 bits and the rest being filled with
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0's.
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### uPC
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The microprogram counter; sometimes also referred to as **MyPC**. This register
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cannot directly be read. It can, though, be written to in a variety of ways.
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These have been specified as *branch* instructions (such as [`BRA`](#bra)), as
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well as subroutine instructions (such as [`ret`](#ret)).
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**NOTE**: This register is not connected to the bus.
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### uSP
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The microstack pointer; sometimes also referred to as **MySPC**. This register
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cannot be directly read or written to. To write to it, a call to a subroutine
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must be issued (using [`call [label]`](#call)). The only way to "read" this
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register is to issue a subroutine-return instruction ([`ret`](#ret)) which
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copies the value in this register to [**uPC**](#upc).
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**NOTE**: This register is not connected to the bus. The value in this register
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cannot be directly acted upon insofar as it cannot be directly read or copied
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to any other register than [**uPC**](#upc), meaning that the actual value in
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this register (and consequently in [**uPC**](#upc) aswell) cannot be directly
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accessed or transformed. I.e. the value in this register cannot be copied to,
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for example, a general register and thus, its value can only be inferred, not
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directly measured.
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## Sorting algorithms
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For the sorting competition, we have chosen to focus on implementing bucketsort
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with an inline insertionsort when inserting values into corresponding buckets.
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