Add Verilog generation flag
This commit is contained in:
Gabriel Tofvesson
parent
96f120a99d
commit
4b88c88a52
11
build.sh
11
build.sh
@ -55,7 +55,12 @@ case $# in
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3)
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if [ "$2" = "asm" ] || [ "$2" = "micro" ]; then
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TYPE=$2
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OUTPUT=$3
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if [ "$3" = "-v" ]; then
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VERILOG=$3
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OUTPUT="build.mia"
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else
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OUTPUT=$3
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fi
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else
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TYPE="asm"
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OUTPUT=$2
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@ -107,12 +112,12 @@ if [ "$COMBINE" = "" ]; then
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kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit
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fi
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kotlin -classpath $(path_of $WEAVER) $WEAVERMAIN $INTER $OUTPUT || exit
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kotlin -classpath $(path_of $WEAVER) $WEAVERMAIN $INTER $OUTPUT $VERILOG || exit
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else
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if [ "$MICRO" != "" ]; then
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kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit
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fi
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kotlin -classpath $(path_of $WEAVERJAR) $WEAVERMAIN $INTER $COMBINE $OUTPUT || exit
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kotlin -classpath $(path_of $WEAVERJAR) $WEAVERMAIN $INTER $COMBINE $OUTPUT $VERILOG || exit
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fi
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# Remove intermediate compilation file
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132
weaver.kt
132
weaver.kt
@ -18,49 +18,88 @@ class MachineState {
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var uSP: Byte = 0.toByte() // SMyPC
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var lc: Byte = 0.toByte() // LC
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override fun toString(): String {
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val builder = StringBuilder("PM:\n")
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for(index in 0 until programMemory.size)
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builder.append(index.toUHex()).append(": ").append(programMemory[index].toUHex()).append("\n")
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override fun toString() = toString(false)
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fun toString(verilog: Boolean): String {
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val builder = StringBuilder()
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if(!verilog) builder.append("PM:\n")
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for(index in 0 until programMemory.size){
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if(verilog) builder.append("initial PM[").append(index).append("] = 16'h")
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else builder.append(index.toUHex()).append(": ")
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builder.append(programMemory[index].toUHex())
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if(verilog) builder.append(';')
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builder.append("\n")
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}
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builder.append("\nMyM:\n")
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for(index in 0 until microMemory.size)
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builder.append(index.toUHex()).append(": ").append(microMemory[index].toShortUHex()).append("\n")
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if(!verilog) builder.append("\nMyM:\n")
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for(index in 0 until microMemory.size){
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if(verilog) builder.append("assign uPM[").append(index).append("] = 25'h")
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else builder.append(index.toUHex()).append(": ")
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builder.append(microMemory[index].toShortUHex())
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if(verilog) builder.append(';')
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builder.append("\n")
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}
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builder.append("\nK1:\n")
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for(index in 0 until k1.size)
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builder.append(index.toUHex()).append(": ").append(k1[index].toUHex()).append("\n")
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if(!verilog) builder.append("\nK1:\n")
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for(index in 0 until k1.size){
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if(verilog) builder.append("assign K1[").append(index).append("] = 7'h")
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else builder.append(index.toUHex()).append(": ")
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builder.append(k1[index].toUHex())
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if(verilog) builder.append(';')
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builder.append("\n")
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}
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builder.append("\nK2:\n")
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for(index in 0 until k2.size)
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builder.append(index.toUHex()).append(": ").append(k2[index].toUHex()).append("\n")
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if(!verilog) builder.append("\nK2:\n")
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for(index in 0 until k2.size){
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if(verilog) builder.append("assign K2[").append(index).append("] = 7'h")
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else builder.append(index.toUHex()).append(": ")
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builder.append(k2[index].toUHex())
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if(verilog) builder.append(';')
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builder.append("\n")
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}
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fun StringBuilder.regSet(name: String, value: Short) =
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if(verilog) append("initial ").append(name).append(" = ").append(value).append(";\n")
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else append('\n').append(name).append(":\n").append(value.toUHex())
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fun StringBuilder.regSet(name: String, value: Byte) =
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if(verilog) append("initial ").append(name).append(" = ").append(value).append(";\n")
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else append('\n').append(name).append(":\n").append(value.toUHex())
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fun StringBuilder.grSet(index: Int, value: Short) =
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if(verilog) append("initial GR[").append(index).append("] = ").append(value).append(";\n")
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else regSet("GR"+index, value)
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fun StringBuilder.irSet(value: Byte) =
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if(verilog) append("initial IR = ").append(value).append(";\n")
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else append("\nIR:\nb").append(value.toInt().or(1 shl 30).toString(2).substring(28))
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fun StringBuilder.uPCSet(value: Byte) =
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if(verilog) append("initial uPC = ").append(value).append(";\n")
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else append("\n\nMyPC:\n").append(value.toUHex())
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fun StringBuilder.uSPSet(value: Byte) =
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if(verilog) append("initial uSP = ").append(value).append(";\n")
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else append("\n\nSMyPC:\n").append(value.toUHex())
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fun StringBuilder.flagInit() =
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if(verilog) this
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else append("\n\nO_flag:\n\nC_flag:\n\nN_flag:\n\nZ_flag:\n\nL_flag:\nEnd_of_dump_file")
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return builder
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.append("\nPC:\n")
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.append(pc.toUHex())
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.append("\n\nASR:\n")
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.append(asr.toUHex())
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.append("\n\nAR:\n")
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.append(ar.toUHex())
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.append("\n\nHR:\n")
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.append(hr.toUHex())
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.append("\n\nGR0:\n")
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.append(gr0.toUHex())
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.append("\n\nGR1:\n")
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.append(gr1.toUHex())
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.append("\n\nGR2:\n")
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.append(gr2.toUHex())
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.append("\n\nGR3:\n")
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.append(gr3.toUHex())
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.append("\n\nIR:\nb")
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.append(ir.toInt().or(1 shl 30).toString(2).substring(28))
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.append("\n\nMyPC:\n")
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.append(uPC.toUHex())
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.append("\n\nSMyPC:\n")
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.append(uSP.toUHex())
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.append("\n\nLC:\n")
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.append(lc.toUHex())
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.append("\n\nO_flag:\n\nC_flag:\n\nN_flag:\n\nZ_flag:\n\nL_flag:\nEnd_of_dump_file")
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.regSet("PC", pc)
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.regSet("ASR", asr)
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.regSet("AR", ar)
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.regSet("HR", hr)
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.grSet(0, gr0)
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.grSet(1, gr1)
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.grSet(2, gr2)
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.grSet(3, gr3)
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.regSet("AR", ar)
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.irSet(ir)
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.uPCSet(uPC)
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.uSPSet(uSP)
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.append('\n').regSet("LC", lc)
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.flagInit()
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.toString()
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}
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@ -110,7 +149,7 @@ fun error(message: String){
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}
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fun main(args: Array<String>){
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if(args.size > 3) error("Too many arguments!")
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if(args.size > 4) error("Too many arguments!")
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if(args.size < 2) error("Too few arguments!")
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val weaveFile = File(args[0])
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@ -118,12 +157,14 @@ fun main(args: Array<String>){
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val state: MachineState
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if(args.size == 2) state = MachineState()
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val verilogOutput = args[args.size - 1] == "-v"
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if(args.size == 2 || (verilogOutput && args.size == 3)) state = MachineState()
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else{
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val file = File(args[1])
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if(file.isFile) state = MachineState.parseState(file.readText())
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else{
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error("Machine state file (${args[1]}) doesn't exist!")
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System.err.println("Machine state file (${args[1]}) doesn't exist! Starting from scratch...")
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state = MachineState()
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}
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}
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@ -196,13 +237,16 @@ fun main(args: Array<String>){
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iIdx()
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}
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val outputFile = if(args.size == 3) File(args[2]) else File(args[1])
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val outputFile = if(!verilogOutput && args.size == 3) File(args[2]) else File(args[1])
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if(outputFile.isFile) outputFile.delete()
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outputFile.createNewFile()
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val machineData = state.toString()
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outputFile.bufferedWriter().use{ it.write(machineData, 0, machineData.length) }
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val machineData = state.toString(verilogOutput)
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outputFile.bufferedWriter().use{
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it.write(machineData, 0, machineData.length)
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it.flush()
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}
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}
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fun Short.toUHex() = toInt().and(0xFFFF.toInt()).or(1.shl(30)).toString(16).substring(4)
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