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Add Verilog generation flag

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Gabriel Tofvesson 2020-03-21 20:13:54 +01:00
parent 96f120a99d
commit 4b88c88a52
2 changed files with 96 additions and 47 deletions
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9
build.sh
View File

@ -55,7 +55,12 @@ case $# in
3) 3)
if [ "$2" = "asm" ] || [ "$2" = "micro" ]; then if [ "$2" = "asm" ] || [ "$2" = "micro" ]; then
TYPE=$2 TYPE=$2
if [ "$3" = "-v" ]; then
VERILOG=$3
OUTPUT="build.mia"
else
OUTPUT=$3 OUTPUT=$3
fi
else else
TYPE="asm" TYPE="asm"
OUTPUT=$2 OUTPUT=$2
@ -107,12 +112,12 @@ if [ "$COMBINE" = "" ]; then
kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit
fi fi
kotlin -classpath $(path_of $WEAVER) $WEAVERMAIN $INTER $OUTPUT || exit kotlin -classpath $(path_of $WEAVER) $WEAVERMAIN $INTER $OUTPUT $VERILOG || exit
else else
if [ "$MICRO" != "" ]; then if [ "$MICRO" != "" ]; then
kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit kotlin -classpath $(path_of $UCOMP) $UCOMPMAIN $MICRO >> $INTER || exit
fi fi
kotlin -classpath $(path_of $WEAVERJAR) $WEAVERMAIN $INTER $COMBINE $OUTPUT || exit kotlin -classpath $(path_of $WEAVERJAR) $WEAVERMAIN $INTER $COMBINE $OUTPUT $VERILOG || exit
fi fi
# Remove intermediate compilation file # Remove intermediate compilation file

132
weaver.kt
View File

@ -18,49 +18,88 @@ class MachineState {
var uSP: Byte = 0.toByte() // SMyPC var uSP: Byte = 0.toByte() // SMyPC
var lc: Byte = 0.toByte() // LC var lc: Byte = 0.toByte() // LC
override fun toString(): String { override fun toString() = toString(false)
val builder = StringBuilder("PM:\n") fun toString(verilog: Boolean): String {
for(index in 0 until programMemory.size) val builder = StringBuilder()
builder.append(index.toUHex()).append(": ").append(programMemory[index].toUHex()).append("\n") if(!verilog) builder.append("PM:\n")
for(index in 0 until programMemory.size){
if(verilog) builder.append("initial PM[").append(index).append("] = 16'h")
else builder.append(index.toUHex()).append(": ")
builder.append(programMemory[index].toUHex())
if(verilog) builder.append(';')
builder.append("\n")
}
builder.append("\nMyM:\n") if(!verilog) builder.append("\nMyM:\n")
for(index in 0 until microMemory.size) for(index in 0 until microMemory.size){
builder.append(index.toUHex()).append(": ").append(microMemory[index].toShortUHex()).append("\n") if(verilog) builder.append("assign uPM[").append(index).append("] = 25'h")
else builder.append(index.toUHex()).append(": ")
builder.append(microMemory[index].toShortUHex())
if(verilog) builder.append(';')
builder.append("\n")
}
builder.append("\nK1:\n") if(!verilog) builder.append("\nK1:\n")
for(index in 0 until k1.size) for(index in 0 until k1.size){
builder.append(index.toUHex()).append(": ").append(k1[index].toUHex()).append("\n") if(verilog) builder.append("assign K1[").append(index).append("] = 7'h")
else builder.append(index.toUHex()).append(": ")
builder.append(k1[index].toUHex())
if(verilog) builder.append(';')
builder.append("\n")
}
builder.append("\nK2:\n") if(!verilog) builder.append("\nK2:\n")
for(index in 0 until k2.size) for(index in 0 until k2.size){
builder.append(index.toUHex()).append(": ").append(k2[index].toUHex()).append("\n") if(verilog) builder.append("assign K2[").append(index).append("] = 7'h")
else builder.append(index.toUHex()).append(": ")
builder.append(k2[index].toUHex())
if(verilog) builder.append(';')
builder.append("\n")
}
fun StringBuilder.regSet(name: String, value: Short) =
if(verilog) append("initial ").append(name).append(" = ").append(value).append(";\n")
else append('\n').append(name).append(":\n").append(value.toUHex())
fun StringBuilder.regSet(name: String, value: Byte) =
if(verilog) append("initial ").append(name).append(" = ").append(value).append(";\n")
else append('\n').append(name).append(":\n").append(value.toUHex())
fun StringBuilder.grSet(index: Int, value: Short) =
if(verilog) append("initial GR[").append(index).append("] = ").append(value).append(";\n")
else regSet("GR"+index, value)
fun StringBuilder.irSet(value: Byte) =
if(verilog) append("initial IR = ").append(value).append(";\n")
else append("\nIR:\nb").append(value.toInt().or(1 shl 30).toString(2).substring(28))
fun StringBuilder.uPCSet(value: Byte) =
if(verilog) append("initial uPC = ").append(value).append(";\n")
else append("\n\nMyPC:\n").append(value.toUHex())
fun StringBuilder.uSPSet(value: Byte) =
if(verilog) append("initial uSP = ").append(value).append(";\n")
else append("\n\nSMyPC:\n").append(value.toUHex())
fun StringBuilder.flagInit() =
if(verilog) this
else append("\n\nO_flag:\n\nC_flag:\n\nN_flag:\n\nZ_flag:\n\nL_flag:\nEnd_of_dump_file")
return builder return builder
.append("\nPC:\n") .regSet("PC", pc)
.append(pc.toUHex()) .regSet("ASR", asr)
.append("\n\nASR:\n") .regSet("AR", ar)
.append(asr.toUHex()) .regSet("HR", hr)
.append("\n\nAR:\n") .grSet(0, gr0)
.append(ar.toUHex()) .grSet(1, gr1)
.append("\n\nHR:\n") .grSet(2, gr2)
.append(hr.toUHex()) .grSet(3, gr3)
.append("\n\nGR0:\n") .regSet("AR", ar)
.append(gr0.toUHex()) .irSet(ir)
.append("\n\nGR1:\n") .uPCSet(uPC)
.append(gr1.toUHex()) .uSPSet(uSP)
.append("\n\nGR2:\n") .append('\n').regSet("LC", lc)
.append(gr2.toUHex()) .flagInit()
.append("\n\nGR3:\n")
.append(gr3.toUHex())
.append("\n\nIR:\nb")
.append(ir.toInt().or(1 shl 30).toString(2).substring(28))
.append("\n\nMyPC:\n")
.append(uPC.toUHex())
.append("\n\nSMyPC:\n")
.append(uSP.toUHex())
.append("\n\nLC:\n")
.append(lc.toUHex())
.append("\n\nO_flag:\n\nC_flag:\n\nN_flag:\n\nZ_flag:\n\nL_flag:\nEnd_of_dump_file")
.toString() .toString()
} }
@ -110,7 +149,7 @@ fun error(message: String){
} }
fun main(args: Array<String>){ fun main(args: Array<String>){
if(args.size > 3) error("Too many arguments!") if(args.size > 4) error("Too many arguments!")
if(args.size < 2) error("Too few arguments!") if(args.size < 2) error("Too few arguments!")
val weaveFile = File(args[0]) val weaveFile = File(args[0])
@ -118,12 +157,14 @@ fun main(args: Array<String>){
val state: MachineState val state: MachineState
if(args.size == 2) state = MachineState() val verilogOutput = args[args.size - 1] == "-v"
if(args.size == 2 || (verilogOutput && args.size == 3)) state = MachineState()
else{ else{
val file = File(args[1]) val file = File(args[1])
if(file.isFile) state = MachineState.parseState(file.readText()) if(file.isFile) state = MachineState.parseState(file.readText())
else{ else{
error("Machine state file (${args[1]}) doesn't exist!") System.err.println("Machine state file (${args[1]}) doesn't exist! Starting from scratch...")
state = MachineState() state = MachineState()
} }
} }
@ -196,13 +237,16 @@ fun main(args: Array<String>){
iIdx() iIdx()
} }
val outputFile = if(args.size == 3) File(args[2]) else File(args[1]) val outputFile = if(!verilogOutput && args.size == 3) File(args[2]) else File(args[1])
if(outputFile.isFile) outputFile.delete() if(outputFile.isFile) outputFile.delete()
outputFile.createNewFile() outputFile.createNewFile()
val machineData = state.toString() val machineData = state.toString(verilogOutput)
outputFile.bufferedWriter().use{ it.write(machineData, 0, machineData.length) } outputFile.bufferedWriter().use{
it.write(machineData, 0, machineData.length)
it.flush()
}
} }
fun Short.toUHex() = toInt().and(0xFFFF.toInt()).or(1.shl(30)).toString(16).substring(4) fun Short.toUHex() = toInt().and(0xFFFF.toInt()).or(1.shl(30)).toString(16).substring(4)