Implement core emulator model
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commit
45f7f961d6
257
MicroEmu.kt
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257
MicroEmu.kt
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class MachineState {
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val programMemory = ShortArray(256) // PM
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val microMemory = IntArray(128) // MyM
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val k1 = ByteArray(16) // K1
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val k2 = ByteArray(4) // K2
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var registers = Registers()
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var flag_Z: Boolean = false
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var flag_N: Boolean = false
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var flag_O: Boolean = false
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var flag_C: Boolean = false
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var flag_L: Boolean = false
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var cycleCount: Long = 0
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var halted: Boolean = false
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fun step(){
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if(halted) return
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++cycleCount
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val instr = microMemory[registers.uPC.toIndexValue()]
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val instr_ALU = instr ushr 21 onlyBits 4
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val instr_TB = instr ushr 18 onlyBits 3
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val instr_FB = instr ushr 15 onlyBits 3
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val instr_S = instr.getBitAt(14)
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val instr_P = instr.getBitAt(13)
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val instr_LC = instr ushr 11 onlyBits 2
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val instr_SEQ = instr ushr 7 onlyBits 4
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val instr_ADR = instr onlyBits 7
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val pInstr = Instruction.parse(registers.ir)
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val mux_select = if(instr_S) pInstr.M else pInstr.GRx
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val gr = when(mux_select.toInt()){
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0 -> registers.gr0
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1 -> registers.gr1
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2 -> registers.gr2
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else -> registers.gr3
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}
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val newRegs = registers.copy()
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val bus_to = when(instr_TB){
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0 -> 0xFFFF.toShort()
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1 -> registers.ir
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2 -> programMemory[registers.asr.toIndexValue()]
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3 -> registers.pc.toMaskedShort()
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4 -> registers.ar
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5 -> registers.hr
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6 -> gr
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else -> instr.onlyBits(16).toShort() // Special TB-mode where uADR is copied to bus
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}
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// Do non-ALU things here
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if(instr_TB != 7){
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when(instr_FB){
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1 -> newRegs.ir = bus_to
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2 -> programMemory[registers.asr.toIndexValue()] = bus_to
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3 -> newRegs.pc = bus_to.toProperType(newRegs.pc)
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5 -> newRegs.hr = bus_to
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6 -> when(mux_select.toInt()){
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0 -> newRegs.gr0 = bus_to
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1 -> newRegs.gr1 = bus_to
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2 -> newRegs.gr2 = bus_to
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else -> newRegs.gr3 = bus_to
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}
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else -> newRegs.asr = bus_to.toProperType(newRegs.asr)
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}
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if(instr_P) newRegs.pc = (registers.pc + 1).toByte()
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when(instr_LC){
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1 -> newRegs.lc = (registers.lc + 1).toByte()
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2 -> newRegs.lc = bus_to.onlyBits(8).toByte()
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3 -> newRegs.lc = instr.onlyBits(8).toByte()
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}
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fun jumpIf(cond: Boolean) =
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if(cond) instr_ADR.toByte()
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else (registers.uPC + 1).toByte()
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newRegs.uPC = when(instr_SEQ){
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0 -> (registers.uPC + 1).toByte()
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1 -> k1[pInstr.OP.toIndexValue()]
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2 -> k2[pInstr.M.toIndexValue()]
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3 -> 0.toByte()
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4 -> jumpIf(!flag_Z)
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5 -> instr_ADR.toByte()
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6 -> {
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newRegs.uSP = registers.uPC
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instr_ADR.toByte()
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}
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7 -> registers.uSP
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8 -> jumpIf(flag_Z)
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9 -> jumpIf(flag_N)
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10 -> jumpIf(flag_C)
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11 -> jumpIf(flag_O)
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12 -> jumpIf(flag_L)
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13 -> jumpIf(!flag_C)
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14 -> jumpIf(!flag_O)
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else -> {
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halted = true
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0.toByte()
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}
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}
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}
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newRegs.ar = when(instr_ALU){
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0 -> registers.ar
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1 -> bus_to
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2 -> bus_to.inv()
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3 ->{
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flag_Z = true
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flag_N = false
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0
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}
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4 ->{
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val result = (registers.ar + bus_to).toShort()
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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flag_C = result <= registers.ar
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flag_O = result.getBitAt(6) != registers.ar.getBitAt(6)
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result
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}
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5 ->{
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val result = (registers.ar + bus_to).toShort()
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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flag_C = result <= registers.ar
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result
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}
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6 ->{
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val result = registers.ar.toInt().and(bus_to.toInt()).toShort()
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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7 ->{
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val result = registers.ar.toInt().or(bus_to.toInt()).toShort()
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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8 -> (registers.ar + bus_to).toShort()
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9 ->{
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val result = registers.ar.toInt().shl(1).toShort()
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flag_C = registers.ar.getBitAt(7)
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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10 ->{
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val result = registers.ar.toInt().shl(16).or(registers.hr.toInt().onlyBits(16)).shl(1)
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newRegs.hr = result.onlyBits(16).toShort()
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flag_C = registers.ar.getBitAt(7)
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flag_Z = result == 0
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flag_N = result < 0
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result.ushr(16).toShort()
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}
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11 ->{
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val result = registers.ar.toInt().shr(1).toShort()
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flag_C = registers.ar.getBitAt(0)
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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12 ->{
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val result = registers.ar.toInt().shl(16).or(registers.hr.toInt().onlyBits(16)).shr(1)
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newRegs.hr = result.onlyBits(16).toShort()
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flag_C = registers.hr.getBitAt(0)
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flag_Z = result == 0
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flag_N = result < 0
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result.ushr(16).toShort()
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}
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13 ->{
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val result = registers.ar.toInt().ushr(1).toShort()
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flag_C = registers.ar.getBitAt(0)
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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14 ->{
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val result = registers.ar.toInt().shl(1).or(registers.ar.toInt().ushr(15)).toShort()
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flag_C = registers.ar.getBitAt(7)
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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else ->{
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val arhr = registers.ar.toInt().shl(16).or(registers.hr.toInt().onlyBits(16))
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val result = arhr.shl(1).or(arhr.ushr(31)).toShort()
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flag_C = registers.hr.getBitAt(0)
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flag_Z = result == 0.toShort()
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flag_N = result < 0
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result
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}
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}
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registers = newRegs
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}
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data class Instruction(
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var OP: Byte = 0,
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var GRx: Byte = 0,
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var M: Byte = 0,
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var adr: Byte = 0
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){
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companion object {
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fun parse(irVal: Short) = Instruction(
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(irVal.toInt() ushr 12 and 15).toByte(),
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(irVal.toInt() ushr 10 and 3).toByte(),
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(irVal.toInt() ushr 8 and 3).toByte(),
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(irVal.toInt() and 255).toByte()
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)
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}
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}
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data class Registers(
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var pc: Byte = 0, // PC
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var asr: Byte = 0, // ASR
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var ar: Short = 0, // AR
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var hr: Short = 0, // HR
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var gr0: Short = 0, // GR0
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var gr1: Short = 0, // GR1
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var gr2: Short = 0, // GR2
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var gr3: Short = 0, // GR3
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var ir: Short = 0, // IR
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var uPC: Byte = 0, // MyPC
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var uSP: Byte = 0, // SMyPC
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var lc: Byte = 0 // LC
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){
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fun copy() = Registers(pc, asr, ar, hr, gr0, gr1, gr2, gr3, ir, uPC, uSP, lc)
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}
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}
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fun Short.inv() = toInt().inv().onlyBits(16).toShort()
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fun Short.onlyBits(bits: Int) = toInt().onlyBits(bits).toShort()
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fun Byte.toMaskedShort() = toProperType(0.toShort())
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fun Short.toProperType(other: Short) = this
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fun Short.toProperType(other: Byte) = toInt().and(0xFF).toByte()
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fun Byte.toProperType(other: Short) = this.toShort()
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fun Byte.toProperType(other: Byte) = this
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fun Byte.toIndexValue() = toInt() and 0xFF
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fun Int.getBitAt(index: Int) = ushr(index).and(1) == 1
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fun Short.getBitAt(index: Int) = toInt().ushr(index).and(1) == 1
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infix fun Int.onlyBits(bits: Int) = and(-1 ushr (32 - bits))
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fun main(args: Array<String>){
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val state = MachineState()
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state.microMemory[0] = 0x2780
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state.step()
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println(state.registers.pc)
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println(state.halted)
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}
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