Continued implementing RAM module

Added VGA test to project

RAM.v

@@ -1,7 +1,7 @@
 module RAM(
 	input  wire         clk,
 	output wire [10:0]  RAM_addr,         // RAM address buffer
-	output wire RAM_A10,
+	output wire         RAM_A10,          // RAM address/auto-precharge
 	output wire [1:0]   RAM_bank_sel,     // RAM bank selection
 	inout  wire [15:0]  RAM_data,         // RAM data bus
 	output wire         RAM_clk,          // RAM clock signal
@@ -16,8 +16,32 @@ module RAM(
 	output wire         op_trigger        // Event trigger wire
 );
 
-always @(posedge clk) begin
+reg [2:0] read_init;                     // Whether or not a read operation has been initiated
+reg       trigger_low;                   // If trigger should be pulled low on next clock cycle
 
+assign op_trigger = read_init == 3'b011;
+assign RAM_enable = ~(read_init != 3'b000);
+assign RAM_clk_enable = read_init != 3'b000;
+
+assign RAM_clk = clk;                    // RAM clock tracks processor input clock
+
+always @(posedge clk) begin
+	if(read_init) begin
+		read_init <= read_init + 3'b001;
+		RAM_state <= 4'b0001;              // STATE: read
+	end
+end
+
+always @(posedge read_rq) begin
+	if(!read_init && !write_rq) begin
+		read_init <= 3'b001;
+	end
+end
+
+always @(posedge write_rq) begin
+	if(!read_init && !read_rq) begin
+		//TODO: Implement read
+	end
 end
 
 endmodule

SevenSegment.v

@@ -72,8 +72,7 @@ VGA screen(clk, gfx_rgb, vga_clk, VGA_rgb, VGA_hsync, VGA_vsync);
 ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
 altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
 
-always @(posedge vga_clk)
-	gfx_rgb <= alu_a[2:0];
+always @(posedge vga_clk) gfx_rgb <= alu_a[2:0];
 
 always @(posedge pll[PLL_SELECT]) begin
 	if(!latch && write && next) begin