GabrielTofvesson/FreeCPU
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GabrielTofvesson e7f9e007d9 Added cache module 
Update VGA module
  Quadrupled pixel clock
  Doubled resolution to 1280x800
Added ZigZag encode/decode to ALU
2018-10-18 03:08:06 +02:00
.gitignore
Added cache module
2018-10-18 03:08:06 +02:00
altpll0_bb.v
Added current Verilog files
2018-10-12 01:23:29 +02:00
altpll0.ppf
Added current Verilog files
2018-10-12 01:23:29 +02:00
altpll0.qip
Added current Verilog files
2018-10-12 01:23:29 +02:00
altpll0.v
Added current Verilog files
2018-10-12 01:23:29 +02:00
ALU.v
Added cache module
2018-10-18 03:08:06 +02:00
cache_bb.v
Added cache module
2018-10-18 03:08:06 +02:00
cache.qip
Added cache module
2018-10-18 03:08:06 +02:00
cache.v
Added cache module
2018-10-18 03:08:06 +02:00
Callback.v
Replaced tabs with spaces
2018-10-17 02:38:17 +02:00
Divider.v
Replaced tabs with spaces
2018-10-17 02:38:17 +02:00
FastAdder.py
Added CLA adder circuit generator
2018-10-12 11:39:08 +02:00
FastMath.v
Added basic VGA graphics support
2018-10-12 16:59:08 +02:00
LICENSE
Initial commit
2018-10-12 01:08:09 +02:00
RAM.v
Fixed comments
2018-10-17 02:46:27 +02:00
README.md
Initial commit
2018-10-12 01:08:09 +02:00
SegmentHexEncoder.v
Replaced tabs with spaces
2018-10-17 02:38:17 +02:00
SegmentManager.v
Replaced tabs with spaces
2018-10-17 02:38:17 +02:00
SevenSegment.v
Added cache module
2018-10-18 03:08:06 +02:00
VDivider.v
Replaced tabs with spaces
2018-10-17 02:38:17 +02:00
VGA.v
Added cache module
2018-10-18 03:08:06 +02:00

README.md

FreeCPU

A CPU described in HDL for the Cyclone IV EP4CE6E22C8N

Description
A CPU described in HDL for the Cyclone IV EP4CE6E22C8N
Readme 72 KiB
Languages
Verilog 99.1%
Python 0.9%