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Fixed comments

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Losslessly truncated register
This commit is contained in:
Gabriel Tofvesson 2018-10-17 02:46:27 +02:00
parent 635158444b
commit 8472077a4b
1 changed files with 17 additions and 17 deletions
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34
RAM.v
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@ -36,11 +36,11 @@ reg [CPB-1:0] acc_cycles; // Cycles used on current bank
reg [1:0] acc_bank; // Which bank is allocating read cycles reg [1:0] acc_bank; // Which bank is allocating read cycles
reg [1:0] acc_close[0:3]; // Requests a close of the current row reg [1:0] acc_close[0:3]; // Requests a close of the current row
reg [3:0] acc_type; // The current access type of the bank (0: READ, 1: WRITE) reg [3:0] acc_type; // The current access type of the bank (0: READ, 1: WRITE)
reg [3:0] acc_state [0:3]; // Current access state for each bank (0: READY, 1: OPENING, 2: tRCD, 3: READ, 4: STOPPING) reg [2:0] acc_state [0:3]; // Current access state for each bank (0: READY, 1: OPENING, 2: tRAS, 3: tRCD, 4: RW_OPEN)
reg [3:0] acc_init_callback; // Pull this high to initiate a callback reg [3:0] acc_init_callback; // Pull this high to initiate a callback
reg [1:0] event_trigger; // Event triggers drive op_trigger reg [1:0] event_trigger; // Event triggers drive op_trigger
wire [3:0] acc_event; // Event update callback wire wire [3:0] acc_event; // Event update callback wire
wire [2:0] callback_timeout[0:3]; // Callback clock cycle definition wire [2:0] callback_timeout[0:3]; // Callback clock cycle definition
Callback #(.ISIZE(3)) cb0(clk, callback_timeout[0], acc_init_callback[0], acc_event[0]); Callback #(.ISIZE(3)) cb0(clk, callback_timeout[0], acc_init_callback[0], acc_event[0]);
@ -71,7 +71,7 @@ integer i;
always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge stop_access or posedge clk) begin always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge stop_access or posedge clk) begin
if(read_rq || write_rq) begin if(read_rq || write_rq) begin
if(acc_state[access_bank] == 4'b0000) begin if(acc_state[access_bank] == 3'b000) begin
RAM_enable <= 1'b0; RAM_enable <= 1'b0;
RAM_strobe_row <= 1'b0; RAM_strobe_row <= 1'b0;
RAM_strobe_col <= 1'b1; RAM_strobe_col <= 1'b1;
@ -81,7 +81,7 @@ always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge sto
RAM_addr <= {address_select[11], address_select[9:0]}; RAM_addr <= {address_select[11], address_select[9:0]};
RAM_A10 <= address_select[10]; RAM_A10 <= address_select[10];
acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1; acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1;
acc_state[access_bank] <= 4'b0001; acc_state[access_bank] <= 3'b001;
acc_init_callback[access_bank] <= 1'b1; acc_init_callback[access_bank] <= 1'b1;
acc_close[access_bank] <= 1'b0; acc_close[access_bank] <= 1'b0;
end end
@ -92,7 +92,7 @@ always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge sto
end end
else if(clk) begin else if(clk) begin
for(i = 0; i < 4; i = i + 1) for(i = 0; i < 4; i = i + 1)
if(acc_state[i] == 4'b0010) if(acc_state[i] == 3'b010)
acc_init_callback[i] <= 1'b1; acc_init_callback[i] <= 1'b1;
if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3])) if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]))
@ -106,22 +106,22 @@ always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge sto
if(acc_close[0]) begin if(acc_close[0]) begin
acc_close[0] <= 1'b0; acc_close[0] <= 1'b0;
RAM_bank_sel <= 2'b00; RAM_bank_sel <= 2'b00;
acc_state[0] <= 4'b0000; acc_state[0] <= 3'b000;
end end
else if(acc_close[1]) begin else if(acc_close[1]) begin
acc_close[1] <= 1'b0; acc_close[1] <= 1'b0;
RAM_bank_sel <= 2'b01; RAM_bank_sel <= 2'b01;
acc_state[1] <= 4'b0000; acc_state[1] <= 3'b000;
end end
else if(acc_close[2]) begin else if(acc_close[2]) begin
acc_close[2] <= 1'b0; acc_close[2] <= 1'b0;
RAM_bank_sel <= 2'b10; RAM_bank_sel <= 2'b10;
acc_state[2] <= 4'b0000; acc_state[2] <= 3'b000;
end end
else if(acc_close[3]) begin else if(acc_close[3]) begin
acc_close[3] <= 1'b0; acc_close[3] <= 1'b0;
RAM_bank_sel <= 2'b11; RAM_bank_sel <= 2'b11;
acc_state[3] <= 4'b0000; acc_state[3] <= 3'b000;
end end
// Increment bank tracker // Increment bank tracker
@ -145,10 +145,10 @@ always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge sto
// Bank_{i+1} at cycle limit and next banks inactive or bank is closing or... // Bank_{i+1} at cycle limit and next banks inactive or bank is closing or...
// Bank_{i+2} at cycle limit and next bank inactive or bank is closing or... // Bank_{i+2} at cycle limit and next bank inactive or bank is closing or...
// Bank_{i+3} at cycle limit or closing // Bank_{i+3} at cycle limit or closing
if(!acc_close[i] && acc_state[i] == 4'b0100 && ( if(!acc_close[i] && acc_state[i] == 3'b100 && (
(acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 4'b0100 && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100))) || (acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 3'b100 && acc_state[(i+2)%4] != 3'b3100 && acc_state[(i+3)%4] != 3'b3100))) ||
(acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100)) || (acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 3'b100 && acc_state[(i+3)%4] != 3'b100)) ||
(acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 4'b0100)) || (acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 3'b100)) ||
(acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}})) (acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}}))
)) begin )) begin
RAM_bank_sel <= i; RAM_bank_sel <= i;
@ -165,18 +165,18 @@ always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge sto
end end
else if(acc_event) begin else if(acc_event) begin
for(i = 0; i < 4; i = i + 1) begin for(i = 0; i < 4; i = i + 1) begin
if(acc_state[i] == 4'b0001) begin if(acc_state[i] == 3'b001) begin
RAM_bank_sel <= i; RAM_bank_sel <= i;
RAM_strobe_row <= 1'b1; RAM_strobe_row <= 1'b1;
RAM_strobe_col <= 1'b0; RAM_strobe_col <= 1'b0;
RAM_write_enable <= ~acc_type[i]; RAM_write_enable <= ~acc_type[i];
RAM_A10 <= 1; RAM_A10 <= 1;
acc_state[i] <= 4'b0010; acc_state[i] <= 3'b010;
acc_init_callback[i] <= 1'b0; acc_init_callback[i] <= 1'b0;
end end
else if(acc_state[i] == 4'b0010) begin else if(acc_state[i] == 3'b010) begin
acc_init_callback[i] <= 1'b0; acc_init_callback[i] <= 1'b0;
acc_state[i] <= 4'b0100; acc_state[i] <= 3'b100;
end end
end end
end end