GabrielTofvesson
e7f9e007d9
Update VGA module Quadrupled pixel clock Doubled resolution to 1280x800 Added ZigZag encode/decode to ALU
56 lines
1.5 KiB
Verilog
56 lines
1.5 KiB
Verilog
module VGA(
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input wire clk,
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input wire [2:0] rgb_data,
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output wire graphics_trigger,
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output wire [11:0] graphics_coords_x,
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output wire [11:0] graphics_coords_y,
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output wire [2:0] VGA_rgb,
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output wire VGA_hsync,
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output wire VGA_vsync
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);
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parameter
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//hsync_end = 10'd95,
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//hdat_begin = 10'd143,
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//hdat_end = 10'd783,
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//hpixel_end = 10'd799,
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//vsync_end = 10'd1,
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//vdat_begin = 10'd34,
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//vdat_end = 10'd514,
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//vline_end = 10'd524;
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hsync_end = 11'd190,
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hdat_begin = 11'd286,
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hdat_end = 11'd1566,
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hpixel_end = 11'd1598,
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vsync_end = 11'd1,
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vdat_begin = 11'd68,
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vdat_end = 11'd1028,
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vline_end = 11'd1048;
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reg [11:0] hcount;
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reg [11:0] vcount;
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wire graphics_clk = clk;
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wire hcount_ov = (hcount == hpixel_end);
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wire vcount_ov = (vcount == vline_end);
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wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));
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assign VGA_hsync = (hcount > hsync_end);
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assign VGA_vsync = (vcount > vsync_end);
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assign VGA_rgb = (dat_act) ? rgb_data : 3'b0;
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assign graphics_coords_x = hcount - hdat_begin;
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assign graphics_coords_y = vcount - vdat_begin;
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assign graphics_trigger = dat_act & graphics_clk;
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// Clock divider
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//always @(posedge clk) graphics_clk = ~graphics_clk;
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// Graphics boundary calculation
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always @(posedge graphics_clk) begin
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if(hcount_ov && vcount_ov) vcount <= 11'b0;
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else if(hcount_ov) vcount <= vcount + 11'b1;
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if (hcount_ov) hcount <= 11'd0;
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else hcount <= hcount + 11'd1;
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end
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endmodule
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