56 lines
1.7 KiB
Verilog
56 lines
1.7 KiB
Verilog
module FastAdder4(
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input wire c_in,
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input wire [3:0] a,
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input wire [3:0] b,
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output wire [3:0] out,
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output wire c_out
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);
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wire [3:0] gen = a & b; // Generator
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wire [3:0] prp = a ^ b; // Propogator
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assign out = a ^ b ^ {
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gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in), // Carry 2
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gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in), // Carry 1
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gen[0] | (prp[0] & c_in), // Carry 0
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c_in // Carry -1 (in)
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};
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assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
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endmodule
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module FastAdder8(
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input wire c_in,
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input wire [7:0] a,
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input wire [7:0] b,
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output wire [7:0] out,
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output wire c_out
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);
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wire [7:0] gen = a & b; // Generator
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wire [7:0] prp = a ^ b; // Propogator
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assign out = a ^ b ^ {
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gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in), // Carry 2
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gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in), // Carry 1
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gen[0] | (prp[0] & c_in), // Carry 0
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c_in // Carry -1 (in)
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};
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assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
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endmodule
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module FastAdder2(
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input wire cin,
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input wire [1:0] a,
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input wire [1:0] b,
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output wire [1:0] out,
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output wire cout
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);
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wire [1:0] g = a & b;
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wire [1:0] p = a ^ b;
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assign out = a ^ b ^ {
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(g[0]) | (p[0] & cin),
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(cin)
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};
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assign cout = (g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin);
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endmodule |