25 lines
618 B
Verilog
25 lines
618 B
Verilog
module SegmentHexEncoder(
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input wire [3:0] number, // Binary number
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output reg [7:0] encoded // Encoded hex output
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);
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always @*
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case(number)
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0: encoded <= 8'hC0;
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1: encoded <= 8'hF9;
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2: encoded <= 8'hA4;
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3: encoded <= 8'hB0;
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4: encoded <= 8'h99;
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5: encoded <= 8'h92;
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6: encoded <= 8'h82;
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7: encoded <= 8'hF8;
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8: encoded <= 8'h80;
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9: encoded <= 8'h98;
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10: encoded <= 8'h88;
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11: encoded <= 8'h83;
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12: encoded <= 8'hC6;
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13: encoded <= 8'hA1;
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14: encoded <= 8'h86;
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default: encoded <= 8'h8E;
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endcase
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endmodule
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