46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
module VGA(
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input wire clk,
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input wire [2:0] rgb_data,
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output reg graphics_clk,
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output wire [9:0] graphics_coords_x,
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output wire [9:0] graphics_coords_y,
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output wire [2:0] VGA_rgb,
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output wire VGA_hsync,
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output wire VGA_vsync
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);
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parameter
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hsync_end = 10'd95,
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hdat_begin = 10'd143,
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hdat_end = 10'd783,
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hpixel_end = 10'd799,
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vsync_end = 10'd1,
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vdat_begin = 10'd34,
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vdat_end = 10'd514,
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vline_end = 10'd524;
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reg [9:0] hcount;
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reg [9:0] vcount;
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wire hcount_ov = (hcount == hpixel_end);
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wire vcount_ov = (vcount == vline_end);
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wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));
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assign VGA_hsync = (hcount > hsync_end);
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assign VGA_vsync = (vcount > vsync_end);
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assign VGA_rgb = (dat_act) ? rgb_data : 3'b0;
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assign graphics_coords_x = vcount;
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assign graphics_coords_y = hcount;
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// Clock divider
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always @(posedge clk) graphics_clk = ~graphics_clk;
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// Graphics boundary calculation
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always @(posedge graphics_clk) begin
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if(hcount_ov && vcount_ov) vcount <= 10'b0;
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else if(hcount_ov) vcount <= vcount + 10'b1;
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if (hcount_ov) hcount <= 10'd0;
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else hcount <= hcount + 10'd1;
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end
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endmodule
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