GabrielTofvesson
8b9bd6e106
Generated some basic FastAdders Generalized FastAdder to include all fast math modules Other minor changes
159 lines
2.5 KiB
Verilog
159 lines
2.5 KiB
Verilog
module ALU(
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] op,
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output wire [7:0] z,
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output wire [7:0] o_flags
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);
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/*
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FLAGS:
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8'bHGFEDCBA
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A: Overflow
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B: Underflow
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C: CMP_GT
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D: CMP_EQ
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E: DIV_BY_0
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F: UNKNWN
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G: N/A
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H: N/A
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*/
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reg [15:0] i_z;
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reg [7:0] i_flg;
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wire [8:0] add_out;
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assign z = i_z[7:0];
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assign o_flags = i_flg;
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FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[7:0]), .cout(add_out[8]));
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always @* begin
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case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
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// ADD
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0: begin
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i_z <= add_out;
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i_flg <= add_out[8] ? 8'b1 : 8'b0; // Set overflow flag if necessary
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end
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// SUB
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1: begin
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i_z <= a-b;
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i_flg <= i_z[15] << 1;
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end
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// MUL
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2: begin
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i_z <= a*b;
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i_flg <= i_z[15:8] != 8'b0 ? 8'b1 : 8'b0;
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end
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// DIV
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3: begin
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if(b != 8'b0) begin
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i_z <= a/b;
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i_flg <= 8'b0;
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end else begin
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i_z <= 16'b0;
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i_flg <= 8'b10000;
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end
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end
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// CMP
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4: begin
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/*
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Flag bits:
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000 -> No output
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001 -> a > b
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010 -> a < b
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011 -> No output
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100 -> a == b
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101 -> a >= b
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110 -> a <= b
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111 -> No output
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*/
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i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 16'b0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 16'b1 : 16'b0;
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i_flg <=
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(a > b ? 8'b100 : 8'b0) | // a > b
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(a == b ? 8'b1000 : 8'b0); // a == b
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end
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// AND
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5: begin
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i_z <= a & b;
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i_flg <= 8'b0;
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end
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// OR
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6: begin
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i_z <= a | b;
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i_flg <= 8'b0;
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end
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// XOR
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7: begin
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i_z <= a ^ b;
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i_flg <= 8'b0;
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end
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// NOT
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8: begin
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i_z <= ~a;
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i_flg <= 8'b0;
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end
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// NAND
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9: begin
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i_z <= ~(a & b);
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i_flg <= 8'b0;
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end
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// NOR
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10: begin
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i_z <= ~(a | b);
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i_flg <= 8'b0;
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end
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// XNOR
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11: begin
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i_z <= ~(a ^ b);
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i_flg <= 8'b0;
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end
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// CL_MUL
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12: begin
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i_z <=
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(a[7] ? b << 7 : 16'b0) ^
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(a[6] ? b << 6 : 16'b0) ^
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(a[5] ? b << 5 : 16'b0) ^
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(a[4] ? b << 4 : 16'b0) ^
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(a[3] ? b << 3 : 16'b0) ^
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(a[2] ? b << 2 : 16'b0) ^
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(a[1] ? b << 1 : 16'b0) ^
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(a[0] ? b : 16'b0);
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i_flg <=
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(a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[6] && (b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[5] && (b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[4] && (b[4] || b[5] || b[6] || b[7])) ||
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(a[3] && (b[5] || b[6] || b[7])) ||
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(a[2] && (b[6] || b[7])) ||
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(a[1] && b[7])
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? 8'b1 : 8'b0;
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end
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default: begin
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i_z <= 16'b0;
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i_flg <= 8'b100000; // Unknown opcode
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end
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endcase
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end
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endmodule
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