371 lines
9.0 KiB
Markdown
371 lines
9.0 KiB
Markdown
# LMIA advanced development kit
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This project was developed as a simple development kit for programming and
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microprogramming the LMIA system.
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## μASM instruction set
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### NOP
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No-operation. This wastes one clock cycle
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### MOV [regA] \[regB\]
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Move value in *regA* to *regB*
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*This operation uses the bus*
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*If regB is LC, no other LC operation can be specified in the same cycle*
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### MVN {[reg] | [const]}
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Move the inverse of a value (from register or constant) into register **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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### MVZ
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Set **AR** to zero.
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*Sets flags: Z, N*
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### ADD {[reg] | [const]}
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Add value (from register or constant) to register **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, O, C*
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### SUB {[reg] | [const]}
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Subtract value (from register or constant) from register **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, O, C*
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### AND {[reg] | [const]}
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Perform bitwise AND with given value (from register or constant) and register
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**AR**. *reg* is ignored and only prevalent due to a microcompiler quirk;
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expect it to be removed in future releases.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N*
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### ORR {[reg] | [const]}
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Perform bitwise Or with given value (from register or constant) and register
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**AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N*
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### ADN {[reg] | [const]}
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Add value (from register or constant) to register **AR** without updating
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flags.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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### LSL
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Performs a logical shift left of **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### BSL
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Performs a logical shift left of **AR** and **HR** as if they were one 32-bit
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register where **AR** corresponds to the most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### ASR
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Performs an arithmetic shift right on **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### BSR
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Performs an arithmetic shift right of **AR** and **HR** as if they were one
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32-bit register where **AR** corresponds to the most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### LSR
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Performs a logical shift right of **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### ROL
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Performs an arithmetic rotate right on **AR**.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### BRL
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Performs an arithmetic shift left of **AR** and **HR** as if they were one
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32-bit register where **AR** corresponds to the most-significant bits.
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*This operation uses the bus*
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*If a constant is passed, this operation cannot be parallellized*
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*Sets flags: Z, N, C*
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### LCSET [const]
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Set **LC** to value of constant.
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### CONST [const]
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Set **AR** to value of cosntant.
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*This operation cannot be parallelized*
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### INCPC
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Increment value in **PC** by one.
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### DECLC
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Decrement value in **LC** by one.
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### CALL [label]
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Move value in **uPC** to **uSP** (**MySPC**) and set value in **uPC** to point
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to the address of the given label.
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### RET
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Move value in **uSP** (**MySPC**) into **uPC**.
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### HALT
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Stop execution and set value int **uPC** to 0.
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### BRA [label]
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Perform an unconditional branch to the address of the given label.
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### BNZ [label]
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Branch to address of label if **Z-flag** is 0.
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### BRZ [label]
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Branch to address of label if **Z-flag** is 1.
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### BRN [label]
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Branch to address of label if **N-flag** is 1.
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### BRC [label]
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Branch to address of label if **C-flag** is 1.
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### BRO [label]
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Branch to address of label if **O-flag** is 1.
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### BLS [label]
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Branch to address of label if **L-flag** is 1.
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### BNC [label]
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Branch to address of label if **C-flag** is 0.
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### BNO [label]
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Branch to address of label if **O-flag** is 0.
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### RESET [reg]
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Sets all bits in the specified register to 1.
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*This operation uses the bus*
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## Compiler/weaver directives
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### \#define \[name] [const]
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Define a compile-time constant. This will replace all (valid) constant
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declarations with the given name with the value supplied here.
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**NOTE**: Constant names are case-insensitive; i.e. *FOO* and *foo* are
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functionally indistinguishable to the compiler.
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### \#data \[address] [const]
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Define an initial value in the program memory at the given address.
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### $[label]
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Define a compile-time label at the given position in the microprogram. Labels
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can be referenced using an '@' symbol.
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For example: *$BAR* would declare a label *BAR* which can be referenced with
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*@BAR*.
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**NOTE**: Label names are case-insensitive; i.e. @*FOO* and @*foo* are
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functionally indistinguishable to the compiler.
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## Flags
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Flags - *aside from L* - are set based on ALU operations, so they depend on
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**AR** and the **BUS**. Henceforth, unless otherwise implied or stated, **AR**
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will refer to the state/value of **AR** *after* an ALU operation.
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### Z
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Set if **AR** == **0**
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### N
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Set if sign bit in **AR** is set.
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### O
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Set if sign of **AR** differs from signs of both **AR** and **BUS** *before*
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the arithmetic operation.
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### C
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Set if **AR** is less than or equal to **AR** *before* the arithmetic
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operation.
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### L
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Set if **LC** == 0.
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## Sorting algorithms
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For the sorting competition, we have chosen to focus on implementing bucketsort
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with an inline insertionsort when inserting values into corresponding buckets.
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### bucksort.uc
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This was the first attempt at a sorting implementation in uASM. It doesn't do
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more than a simple hash and possibly updating some bucket-specific values.
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Nonetheless, it formed a clear basis for future implementations.
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Pros:
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* N/A
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Cons:
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* N/A
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Average cycle count: N/A
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### bsrt.uc
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The first successful uASM bucketsort implementation. It uses the aforementioned
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inline insertionsort. Additionally, it employs a lookup table for pointing to
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buckets; this had the benefit of significantly decreasing the cycles required
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to hash values, as well as allowing for buckets of sizes other than even
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exponents of 2 (as opposed to other implementations). On top of this, it used a
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parallel-hashing system which allowed the rotation step of the hash algorithm
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to be applied to two elements of the list (to be sorted) at once, further
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decreasing the amount of cycles required to perform a hash (per element).
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Pros:
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* Variable bucket size
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* Arbitrary bucket arrangement
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* Parallel-hash implementation
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* Uses the most recent merge algorithm (rated around 400 cycles)
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Cons:
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* Heavy bookkeeping due to lookup table paired with parallel-hash
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* Inefficiency in merge due to lookup table (average loss of 80 cycles)
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Average cycle count: 1250
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### sort2.uc
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A second iteration of the *bsrt* implementation, this one refines the dual-hash
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by omitting the lookup table. This means that bookkeeping can be minimized, as
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it was only necessary due to a lack of available registers. This, of course,
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comes at the cost of not being able to have variable-sized buckets; i.e. their
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sizes must an exponent of 2. A minor optimization that was created for this
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algorithm was the hash-based bookkeeping, wherein a small optimization to
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bookkeeping could be done during the hashing of the list elements. Any
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bookkeeping which does not require the ALU can, in fact, be performed during the
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hashing, since the rotation steps only require AR and HR to be untouched. All
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other operations are permitted.
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Pros:
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* Merge: (320-330 cycles)
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* Direct addressing fits optimally due to register limitations
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* Optimized regster allocations
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* Minimal bookkeeping since it is mostly performed during the hashing operation
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Cons:
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* Bucket sizes must be exponents of 2
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* Fixed bucket indices based on hash
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* Two merge operations required (negative + positive)
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* 95 unused program-memory addresses
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Average cycle count: 1100
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### sort3.uc
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A third iteration of the *bsrt* implementation: this time entirely scrapping
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the bucket header, opting to delegate this behaviour to the lookup-table itself.
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I.e. the lookup table no long points to the start of a bucket (as this can be
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inferred later), but rather points to the last element of the bucket.
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Additionally, this implementation scraps the insertion-sort performed in the
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bucket sort, delegating this task to the merge stage of the sorting algorithm.
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Pros:
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* Constant-time bucket sort (406 cycles)
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* More optimally used LUT
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* No bookkeeping during bucket-sort
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Cons:
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* Non-constant-time merge
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* Optimized LUT requires marginally more arithmetic operations over other variants
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Average cycle count: N/A (not fully implemented)
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