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Changed clock source for test callback module due to stability issues

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Gabriel Tofvesson 2018-10-15 09:27:23 +02:00
parent 41f95d2077
commit 026def0a26
2 changed files with 4 additions and 4 deletions
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4
Callback.v
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@ -8,7 +8,7 @@ module Callback(
parameter ISIZE; parameter ISIZE;
reg [ISIZE-1:0] counter; reg [ISIZE-1:0] counter;
reg [1:0] ctr_trigger = 2'b10; reg [2:0] ctr_trigger = 2'b10;
assign callback = !counter & ctr_trigger; assign callback = !counter & ctr_trigger;
@ -18,7 +18,7 @@ always @(posedge clk or posedge reset) begin
ctr_trigger <= 2'b10; ctr_trigger <= 2'b10;
end end
else if(counter) counter <= counter - 1'b1; else if(counter) counter <= counter - 1'b1;
else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b01; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
end end
endmodule endmodule

4
SevenSegment.v
View File

@ -84,8 +84,8 @@ ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
// Clock generator // Clock generator
altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]); altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
// Callback module (generate timeouts) (Precision: 1/400M = 2.5ns) // Callback module (generate timeouts) (Precision: 1/100M = 10ns) NOTE: 400MHz seems to be unstable, so a precision of 2.5ns comes at the price of stability
Callback #(.ISIZE(32)) timeout(pll[3], 32'd400000000, ~value, cb); Callback #(.ISIZE(32)) timeout(pll[0], 32'd100000000, ~value, cb);
// RAM module // RAM module
RAM main_memory( RAM main_memory(