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Started implementing RAM bank parallelization

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Gabriel Tofvesson 2018-10-15 09:47:11 +02:00
parent 026def0a26
commit 30ceb1f2ce
2 changed files with 29 additions and 21 deletions
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22
RAM.v
View File

@ -12,11 +12,12 @@ module RAM(
output wire RAM_write_enable, // RAM data bus write enable
input wire read_rq, // Read request (Internal)
input wire write_rq, // Write request (Internal)
output reg [3:0] RAM_state, // State information (Internal)
output wire op_trigger // Event trigger wire
input wire [1:0] access_bank, // Which bank to access
output reg [15:0] RAM_state, // State information (Internal)
output wire [3:0] op_trigger // Event trigger wire (per bank)
);
reg [2:0] read_init; // Whether or not a read operation has been initiated
reg [2:0] read_init[0:3]; // Whether or not a read operation has been initiated
reg trigger_low; // If trigger should be pulled low on next clock cycle
assign op_trigger = read_init == 3'b011;
@ -25,16 +26,21 @@ assign RAM_clk_enable = read_init != 3'b000;
assign RAM_clk = clk; // RAM clock tracks processor input clock
integer i;
always @(posedge clk or posedge read_rq) begin
if(read_rq) begin
if(!read_init && !write_rq) begin
read_init <= 3'b001;
read_init[access_bank] <= 3'b001;
end
end
else if(read_init) begin
read_init <= read_init + 3'b001;
RAM_state <= 4'b0001; // STATE: read
end
else begin
for(i = 0; i<4; i = i + 1)
if(read_init[i]) begin
read_init[i] <= read_init[i] + 3'b001; // Increment read
RAM_state[i*3 + 3 : i*3] <= 4'b0001; // STATE: read
end
end
end
always @(posedge write_rq) begin

28
SevenSegment.v
View File

@ -24,8 +24,8 @@ module SevenSegment(
);
// ---- SETTINGS ---- //
localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!!
localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!!
// ---- REGISTERS ---- //
reg debounce; // Input debouncer
@ -36,19 +36,20 @@ reg [7:0] alu_a; // ALU (core0) input a
reg [7:0] alu_b; // ALU (core0) input b
reg [7:0] alu_op; // ALU (core0) opcode
reg [2:0] gfx_rgb; // VGA color channels
reg [1:0] ram_bank_sel; // Which ram bank to access
// ---- WIRES ---- //
wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer)
wire [7:0] alu_out; // ALU (core0) output
wire [7:0] alu_flags; // ALU (core0) output flags
wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
wire vga_clk; // VGA data clock
wire cb; // Callback/timeout
wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to
wire ram_request_read; // Trigger a read operation from main memory
wire ram_request_write; // Trigger a write operation from main memory
wire ram_event; // Event trigger from ram when an operation is completed (ex. a read op is ready)
wire [3:0] ram_state; // Main memory event information
wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer)
wire [7:0] alu_out; // ALU (core0) output
wire [7:0] alu_flags; // ALU (core0) output flags
wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
wire vga_clk; // VGA data clock
wire cb; // Callback/timeout
wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to
wire ram_request_read; // Trigger a read operation from main memory
wire ram_request_write; // Trigger a write operation from main memory
wire [3:0] ram_event; // Event trigger from ram when an operation is completed (ex. a read op is ready)
wire [15:0] ram_state; // Main memory event information (0:3; bank0, 4:7; bank1, 8:11; bank2, 12:15; bank3)
// ---- WIRE ASSIGNS ---- //
assign pll[4] = clk;
@ -102,6 +103,7 @@ RAM main_memory(
RAM_write_enable,
ram_request_read,
ram_request_write,
ram_bank_sel,
ram_state,
ram_event
);