53 lines
1.9 KiB
Verilog
53 lines
1.9 KiB
Verilog
module RAM(
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input wire clk,
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output wire [10:0] RAM_addr, // RAM address buffer
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output wire RAM_A10, // RAM address/auto-precharge
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output wire [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output wire RAM_enable, // RAM chip enable
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output wire RAM_strobe_row, // RAM row strobe
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output wire RAM_strobe_col, // RAM column strobe
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output wire RAM_write_enable, // RAM data bus write enable
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input wire read_rq, // Read request (Internal)
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input wire write_rq, // Write request (Internal)
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input wire [1:0] access_bank, // Which bank to access
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output reg [15:0] RAM_state, // State information (Internal)
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output wire [3:0] op_trigger // Event trigger wire (per bank)
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);
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reg [2:0] read_init[0:3]; // Whether or not a read operation has been initiated
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reg trigger_low; // If trigger should be pulled low on next clock cycle
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assign op_trigger = read_init == 3'b011;
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assign RAM_enable = ~(read_init != 3'b000);
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assign RAM_clk_enable = read_init != 3'b000;
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assign RAM_clk = clk; // RAM clock tracks processor input clock
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integer i;
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always @(posedge clk or posedge read_rq) begin
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if(read_rq) begin
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if(!read_init && !write_rq) begin
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read_init[access_bank] <= 3'b001;
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end
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end
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else begin
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for(i = 0; i<4; i = i + 1)
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if(read_init[i]) begin
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read_init[i] <= read_init[i] + 3'b001; // Increment read
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RAM_state[i*3 + 3 : i*3] <= 4'b0001; // STATE: read
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end
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end
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end
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always @(posedge write_rq) begin
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if(!read_init && !read_rq) begin
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//TODO: Implement read
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end
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end
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endmodule
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