3 Commits

Author	SHA1	Message	Date
GabrielTofvesson	e7f9e007d9	Added cache module ... Update VGA module Quadrupled pixel clock Doubled resolution to 1280x800 Added ZigZag encode/decode to ALU	2018-10-18 03:08:06 +02:00
GabrielTofvesson	8b9bd6e106	Added basic VGA graphics support ... Generated some basic FastAdders Generalized FastAdder to include all fast math modules Other minor changes	2018-10-12 16:59:08 +02:00
GabrielTofvesson	1126ce5582	Added current Verilog files	2018-10-12 01:23:29 +02:00