GabrielTofvesson/FreeCPU
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  • e7f9e007d9 Added cache module Update VGA module Quadrupled pixel clock Doubled resolution to 1280x800 Added ZigZag encode/decode to ALU master GabrielTofvesson 2018-10-18 03:08:06 +02:00
  • 8472077a4b Fixed comments Losslessly truncated register GabrielTofvesson 2018-10-17 02:46:27 +02:00
  • 635158444b Replaced tabs with spaces GabrielTofvesson 2018-10-17 02:38:17 +02:00
  • a3f7a48276 Fixed minor issues in ALU.v Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging GabrielTofvesson 2018-10-17 02:34:03 +02:00
  • 7ebac10ffc
         Delete SDRAM.v Gabriel Tofvesson 2018-10-15 11:35:38 +02:00
  • 10d33a514f Made ALU parameter bit width variable Removed CL_MUL operation due to complications with variable-sized inputs Fixed RAM implementation issues GabrielTofvesson 2018-10-15 11:34:50 +02:00
  • 30ceb1f2ce Started implementing RAM bank parallelization GabrielTofvesson 2018-10-15 09:47:11 +02:00
  • 026def0a26 Changed clock source for test callback module due to stability issues GabrielTofvesson 2018-10-15 09:27:23 +02:00
  • 41f95d2077 Added shift/rotate operations to ALU Added callback/timeout module Added pixel location output to VGA module Fixed state management for RAM module Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable GabrielTofvesson 2018-10-15 09:21:03 +02:00
  • 4642890198 Continued implementing RAM module Added VGA test to project GabrielTofvesson 2018-10-12 23:27:25 +02:00
  • 8b9bd6e106 Added basic VGA graphics support Generated some basic FastAdders Generalized FastAdder to include all fast math modules Other minor changes GabrielTofvesson 2018-10-12 16:59:08 +02:00
  • 571a280d3e Added CLA adder circuit generator GabrielTofvesson 2018-10-12 11:39:08 +02:00
  • 1126ce5582 Added current Verilog files GabrielTofvesson 2018-10-12 01:23:29 +02:00
  • 4f1a53847c
         Initial commit Gabriel Tofvesson 2018-10-12 01:08:09 +02:00