2 Commits

Author SHA1 Message Date
026def0a26 Changed clock source for test callback module due to stability issues 2018-10-15 09:27:23 +02:00
41f95d2077 Added shift/rotate operations to ALU
Added callback/timeout module
Added pixel location output to VGA module
Fixed state management for RAM module
Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable
2018-10-15 09:21:03 +02:00