24 lines
774 B
Verilog
24 lines
774 B
Verilog
module RAM(
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input wire clk,
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output wire [10:0] RAM_addr, // RAM address buffer
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output wire RAM_A10,
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output wire [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output wire RAM_enable, // RAM chip enable
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output wire RAM_strobe_row, // RAM row strobe
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output wire RAM_strobe_col, // RAM column strobe
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output wire RAM_write_enable, // RAM data bus write enable
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input wire read_rq, // Read request (Internal)
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input wire write_rq, // Write request (Internal)
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output reg [3:0] RAM_state, // State information (Internal)
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output wire op_trigger // Event trigger wire
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);
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always @(posedge clk) begin
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end
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endmodule
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