35 lines
1.2 KiB
Verilog
35 lines
1.2 KiB
Verilog
module SegmentManager(
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input wire clk, // 50MHz clock signal
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input wire [7:0] segment_data0, // Segment data for segment 0 (D1)
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input wire [7:0] segment_data1, // Segment data for segment 1 (D2)
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input wire [7:0] segment_data2, // Segment data for segment 2 (D3)
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input wire [7:0] segment_data3, // Segment data for segment 3 (D4)
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output reg [3:0] segment_select, // 7-segment display selector
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output reg [7:0] segments // Segment display bus
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);
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initial segment_select = 4'b1110;
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reg [1:0] seg_sel_track; // Active display tracker
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wire clk_graphics; // Internal clock divider output
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// Clock division circuit
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Divider #(.divideby(25000), .divide_reg_size(17)) divider_audio(clk, clk_graphics); // Frequency: 50MHz/25k = 2kHz TriggerType: Pulse
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// Change the active segment data
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always @(posedge clk_graphics) begin
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segment_select <=(segment_select << 1) | segment_select[3];
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seg_sel_track <= seg_sel_track + 1;
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end
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// Assign the active segment data to the segment bus
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always @*
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case(seg_sel_track)
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0: segments <= segment_data0;
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1: segments <= segment_data1;
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2: segments <= segment_data2;
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default: segments <= segment_data3;
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endcase
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endmodule
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