28 lines
617 B
Verilog
28 lines
617 B
Verilog
module VDivider(
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input wire clk, // Clock input
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input wire [divide_reg_size-1:0] compare_to,
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output wire divided // Divided output
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);
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// Parameters for division circuit
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parameter divide_reg_size;
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parameter pulsemode = 1;
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reg [divide_reg_size-1:0] div; // Division counter
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reg div_int; // Internal division result state
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assign divided = div_int; // Assign internal result state to external output
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// Division
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always @ (posedge clk) begin
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if(div >= compare_to) begin
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div_int <= pulsemode ? 1 : ~div_int;
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div <= 0;
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end else begin
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if(pulsemode) div_int <= 0;
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div <= div + 1;
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end
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end
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endmodule
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