Made ALU parameter bit width variable

Removed CL_MUL operation due to complications with variable-sized inputs
Fixed RAM implementation issues

ALU.v

@@ -1,11 +1,14 @@
 module ALU(
-   input wire [7:0] a,
+   input wire [BITS-1:0] a,
-   input wire [7:0] b,
+   input wire [BITS-1:0] b,
-   input wire [7:0] op,
+   input wire [BITS-1:0] op,
-   output wire [7:0] z,
+   output wire [BITS-1:0] z,
    output wire [7:0] o_flags
 );
 
+parameter BITS;
+parameter LOG2_BITS;
+
 /*
 FLAGS:
 
@@ -22,25 +25,35 @@ H: N/A
 
 */
 
-reg [15:0] i_z;
+reg [(BITS*2)-1:0] i_z;
 reg [7:0]  i_flg;
 reg        shift_rotate;
 
-wire [8:0] add_out;
+wire [BITS:0]      add_out;
-wire [7:0] lshift[0:2];
+wire [BITS-1:0]    lshift [0:LOG2_BITS];
-wire       lshift_overflow[0:2];
+wire [LOG2_BITS:0] lshift_overflow;
-wire [7:0] rshift[0:2];
+wire [BITS-1:0]    rshift [0:LOG2_BITS];
-wire       rshift_underflow[0:2];
+wire [LOG2_BITS:0] rshift_underflow;
 
 assign z = i_z[7:0];
 assign o_flags = i_flg;
 
-FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[7:0]), .cout(add_out[8]));
+FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[BITS-1:0]), .cout(add_out[BITS]));
+
+genvar i;
+generate
+   for(i = 1; i<LOG2_BITS; i = i + 1) begin : shifters
+      LeftBitShifter #(.bits(BITS), .shiftby(2**(i-1))) lsh(i==1 ? a : lshift[i-1], b[i], shift_rotate, lshift[i], lshift_overflow[i]);
+		RightBitShifter #(.bits(BITS), .shiftby(2**(i-1))) rsh(i==1 ? a : rshift[i-1], b[i], shift_rotate, rshift[i], rshift_underflow[i]);
+   end
+endgenerate
+
+integer j;
 
 // Left shift decoder
-LeftBitShifter #(.bits(8), .shiftby(1)) (a, b[0], shift_rotate, lshift[0], lshift_overflow[0]);
+//LeftBitShifter #(.bits(BITS), .shiftby(1)) (a, b[0], shift_rotate, lshift[0], lshift_overflow[0]);
-LeftBitShifter #(.bits(8), .shiftby(2)) (lshift[0], b[1], shift_rotate, lshift[1], lshift_overflow[1]);
+//LeftBitShifter #(.bits(BITS), .shiftby(2)) (lshift[0], b[1], shift_rotate, lshift[1], lshift_overflow[1]);
-LeftBitShifter #(.bits(8), .shiftby(4)) (lshift[1], b[2], shift_rotate, lshift[2], lshift_overflow[2]);
+//LeftBitShifter #(.bits(BITS), .shiftby(4)) (lshift[1], b[2], shift_rotate, lshift[2], lshift_overflow[2]);
 //LeftBitShifter #(.bits(8), .shiftby(8)) (lshift[2], b[3], lshift[3], lshift_overflow[3]);
 //LeftBitShifter #(.bits(8), .shiftby(16)) (lshift[3], b[4], lshift[4], lshift_overflow[4]);
 //LeftBitShifter #(.bits(8), .shiftby(32)) (lshift[4], b[5], lshift[5], lshift_overflow[5]);
@@ -48,9 +61,9 @@ LeftBitShifter #(.bits(8), .shiftby(4)) (lshift[1], b[2], shift_rotate, lshift[2
 //LeftBitShifter #(.bits(8), .shiftby(128)) (lshift[6], b[7], lshift[7], lshift_overflow[7]);
 
 // Right shift decoder
-RightBitShifter #(.bits(8), .shiftby(1)) (a, b[0], shift_rotate, rshift[0], rshift_underflow[0]);
+//RightBitShifter #(.bits(BITS), .shiftby(1)) (a, b[0], shift_rotate, rshift[0], rshift_underflow[0]);
-RightBitShifter #(.bits(8), .shiftby(2)) (rshift[0], b[1], shift_rotate, rshift[1], rshift_underflow[1]);
+//RightBitShifter #(.bits(BITS), .shiftby(2)) (rshift[0], b[1], shift_rotate, rshift[1], rshift_underflow[1]);
-RightBitShifter #(.bits(8), .shiftby(4)) (rshift[1], b[2], shift_rotate, rshift[2], rshift_underflow[2]);
+//RightBitShifter #(.bits(BITS), .shiftby(4)) (rshift[1], b[2], shift_rotate, rshift[2], rshift_underflow[2]);
 //RightBitShifter #(.bits(8), .shiftby(8)) (rshift[2], b[3], rshift[3], rshift_underflow[3]);
 //RightBitShifter #(.bits(8), .shiftby(16)) (rshift[3], b[4], rshift[4], rshift_underflow[4]);
 //RightBitShifter #(.bits(8), .shiftby(32)) (rshift[4], b[5], rshift[5], rshift_underflow[5]);
@@ -62,28 +75,28 @@ always @* begin
       // ADD
       0: begin
          i_z <= add_out;
-         i_flg <= add_out[8] ? 8'b1 : 8'b0; // Set overflow flag if necessary
+         i_flg <= add_out[BITS] ? 8'b1 : 8'b0; // Set overflow flag if necessary
       end
       
       // SUB
       1: begin
          i_z <= a-b;
-         i_flg <= i_z[15] << 1;
+         i_flg <= {i_z[BITS*2 - 1], 1'b0};
       end
       
       // MUL
       2: begin
          i_z <= a*b;
-         i_flg <= i_z[15:8] != 8'b0 ? 8'b1 : 8'b0;
+         i_flg <= i_z[BITS*2 - 1:BITS] != {BITS{1'b0}} ? 8'b1 : 8'b0;
       end
       
       // DIV
       3: begin
-         if(b != 8'b0) begin
+         if(b != {BITS{1'b0}}) begin
             i_z <= a/b;
             i_flg <= 8'b0;
          end else begin
-            i_z <= 16'b0;
+            i_z <= {{BITS{1'b0}}, {BITS{1'b0}}};
             i_flg <= 8'b10000;
          end
       end
@@ -152,6 +165,7 @@ always @* begin
       end
       
       // CL_MUL
+		/*
       12: begin
          i_z <=
             (a[7] ? b << 7 : 16'b0) ^
@@ -173,22 +187,23 @@ always @* begin
             (a[1] && b[7])
             ? 8'b1 : 8'b0;
       end
+      */
 		
       // SHR (flag: rotate)
       13: begin
          shift_rotate <= op[5];
-         i_z   <= b >= 8 ? 16'b0 : rshift[2];
+         i_z   <= b >= BITS ? {BITS{1'b0}} : rshift[LOG2_BITS-1];
-         i_flg <= rshift_underflow[0] || rshift_underflow[1] || rshift_underflow[2] || (b >= 8) ? 8'b10: 8'b0;
+         i_flg <= rshift_underflow || (b >= BITS) ? 8'b10: 8'b0;
       end
       
       // SHL (flag: rotate)
       14: begin
          shift_rotate <= op[5];
-         i_z   <= b >= 8 ? 16'b0 : lshift[2];
+         i_z   <= b >= BITS ? {BITS{1'b0}} : lshift[LOG2_BITS-1];
-         i_flg <= lshift_overflow[0] || lshift_overflow[1] || lshift_overflow[2] || (b >= 8) ? 8'b1 : 8'b0;
+         i_flg <= lshift_overflow || (b >= BITS) ? 8'b1 : 8'b0;
       end
       default: begin
-         i_z <= 16'b0;
+         i_z <= {BITS{1'b0}};
          i_flg <= 8'b100000; // Unknown opcode
       end
    endcase
@@ -227,3 +242,13 @@ assign underflow = doshift && data[shiftby:0] ? 1'b1 : 1'b0;
 assign out = doshift ? {rotate ? data[shiftby-1:0] : {shiftby{1'b0}}, data[bits-1:shiftby]} : data;
 
 endmodule
+
+module Combine(
+    input wire  i1,
+	 input wire  i2,
+	 output wire o
+);
+
+assign o = i1 | i2;
+
+endmodule

RAM.v

@@ -20,9 +20,15 @@ module RAM(
 reg [2:0] read_init[0:3];                // Whether or not a read operation has been initiated
 reg       trigger_low;                   // If trigger should be pulled low on next clock cycle
 
-assign op_trigger = read_init == 3'b011;
+genvar k;
-assign RAM_enable = ~(read_init != 3'b000);
+generate
-assign RAM_clk_enable = read_init != 3'b000;
+   for(k = 0; k<4; k = k + 1) begin : trigger_gen
+      assign op_trigger[k] = read_init[k] == 3'b011;
+   end
+endgenerate
+
+assign RAM_enable = read_init[0] == 3'b000 && read_init[1] == 3'b000 && read_init[2] == 3'b000 && read_init[3] == 3'b000;
+assign RAM_clk_enable = read_init[0] != 3'b000 && read_init[1] != 3'b000 && read_init[2] != 3'b000 && read_init[3] != 3'b000;
 
 assign RAM_clk = clk;                    // RAM clock tracks processor input clock
 
@@ -30,21 +36,32 @@ integer i;
 
 always @(posedge clk or posedge read_rq) begin
    if(read_rq) begin
-      if(!read_init && !write_rq) begin
+      if(!read_init[access_bank] && !write_rq) begin
          read_init[access_bank] <= 3'b001;
       end
 	end
    else begin
-		for(i = 0; i<4; i = i + 1)
+		if(read_init[0]) begin
-		   if(read_init[i]) begin
+         read_init[0] <= read_init[0] + 3'b001; // Increment read
-            read_init[i] <= read_init[i] + 3'b001; // Increment read
+         RAM_state[3:0] <= 4'b0001;   // STATE: read
-            RAM_state[i*3 + 3 : i*3] <= 4'b0001;   // STATE: read
+      end
-         end
+		if(read_init[1]) begin
+         read_init[1] <= read_init[1] + 3'b001; // Increment read
+         RAM_state[7:4] <= 4'b0001;   // STATE: read
+      end
+		if(read_init[2]) begin
+         read_init[2] <= read_init[2] + 3'b001; // Increment read
+         RAM_state[11:8] <= 4'b0001;   // STATE: read
+      end
+		if(read_init[3]) begin
+         read_init[3] <= read_init[3] + 3'b001; // Increment read
+         RAM_state[15:12] <= 4'b0001;   // STATE: read
+      end
 	end
 end
 
 always @(posedge write_rq) begin
-	if(!read_init && !read_rq) begin
+	if(!read_init[access_bank] && !read_rq) begin
       //TODO: Implement read
 	end
 end

SevenSegment.v

@@ -80,7 +80,7 @@ SegmentManager seg_display(
 VGA screen(clk, gfx_rgb, vga_clk, vga_coords[0], vga_coords[1], VGA_rgb, VGA_hsync, VGA_vsync);
 
 // Arithmetic logic unit
-ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
+ALU #(.BITS(8), .LOG2_BITS(3)) core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
 
 // Clock generator
 altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);