Added shift/rotate operations to ALU
Added callback/timeout module Added pixel location output to VGA module Fixed state management for RAM module Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable
This commit is contained in:
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4642890198
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41f95d2077
323
ALU.v
323
ALU.v
@ -1,9 +1,9 @@
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module ALU(
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module ALU(
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input wire [7:0] a,
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input wire [7:0] a,
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input wire [7:0] b,
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input wire [7:0] b,
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input wire [7:0] op,
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input wire [7:0] op,
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output wire [7:0] z,
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output wire [7:0] z,
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output wire [7:0] o_flags
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output wire [7:0] o_flags
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);
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);
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/*
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/*
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@ -23,136 +23,207 @@ H: N/A
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*/
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*/
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reg [15:0] i_z;
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reg [15:0] i_z;
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reg [7:0] i_flg;
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reg [7:0] i_flg;
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reg shift_rotate;
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wire [8:0] add_out;
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wire [8:0] add_out;
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wire [7:0] lshift[0:2];
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wire lshift_overflow[0:2];
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wire [7:0] rshift[0:2];
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wire rshift_underflow[0:2];
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assign z = i_z[7:0];
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assign z = i_z[7:0];
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assign o_flags = i_flg;
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assign o_flags = i_flg;
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FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[7:0]), .cout(add_out[8]));
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FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[7:0]), .cout(add_out[8]));
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// Left shift decoder
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LeftBitShifter #(.bits(8), .shiftby(1)) (a, b[0], shift_rotate, lshift[0], lshift_overflow[0]);
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LeftBitShifter #(.bits(8), .shiftby(2)) (lshift[0], b[1], shift_rotate, lshift[1], lshift_overflow[1]);
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LeftBitShifter #(.bits(8), .shiftby(4)) (lshift[1], b[2], shift_rotate, lshift[2], lshift_overflow[2]);
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//LeftBitShifter #(.bits(8), .shiftby(8)) (lshift[2], b[3], lshift[3], lshift_overflow[3]);
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//LeftBitShifter #(.bits(8), .shiftby(16)) (lshift[3], b[4], lshift[4], lshift_overflow[4]);
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//LeftBitShifter #(.bits(8), .shiftby(32)) (lshift[4], b[5], lshift[5], lshift_overflow[5]);
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//LeftBitShifter #(.bits(8), .shiftby(64)) (lshift[5], b[6], lshift[6], lshift_overflow[6]);
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//LeftBitShifter #(.bits(8), .shiftby(128)) (lshift[6], b[7], lshift[7], lshift_overflow[7]);
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// Right shift decoder
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RightBitShifter #(.bits(8), .shiftby(1)) (a, b[0], shift_rotate, rshift[0], rshift_underflow[0]);
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RightBitShifter #(.bits(8), .shiftby(2)) (rshift[0], b[1], shift_rotate, rshift[1], rshift_underflow[1]);
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RightBitShifter #(.bits(8), .shiftby(4)) (rshift[1], b[2], shift_rotate, rshift[2], rshift_underflow[2]);
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//RightBitShifter #(.bits(8), .shiftby(8)) (rshift[2], b[3], rshift[3], rshift_underflow[3]);
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//RightBitShifter #(.bits(8), .shiftby(16)) (rshift[3], b[4], rshift[4], rshift_underflow[4]);
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//RightBitShifter #(.bits(8), .shiftby(32)) (rshift[4], b[5], rshift[5], rshift_underflow[5]);
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//RightBitShifter #(.bits(8), .shiftby(64)) (rshift[5], b[6], rshift[6], rshift_underflow[6]);
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//RightBitShifter #(.bits(8), .shiftby(128)) (rshift[6], b[7], rshift[7], rshift_underflow[7]);
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always @* begin
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always @* begin
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case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
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case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
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// ADD
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// ADD
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0: begin
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0: begin
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i_z <= add_out;
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i_z <= add_out;
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i_flg <= add_out[8] ? 8'b1 : 8'b0; // Set overflow flag if necessary
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i_flg <= add_out[8] ? 8'b1 : 8'b0; // Set overflow flag if necessary
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end
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end
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// SUB
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// SUB
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1: begin
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1: begin
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i_z <= a-b;
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i_z <= a-b;
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i_flg <= i_z[15] << 1;
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i_flg <= i_z[15] << 1;
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end
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end
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// MUL
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// MUL
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2: begin
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2: begin
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i_z <= a*b;
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i_z <= a*b;
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i_flg <= i_z[15:8] != 8'b0 ? 8'b1 : 8'b0;
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i_flg <= i_z[15:8] != 8'b0 ? 8'b1 : 8'b0;
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end
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end
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// DIV
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// DIV
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3: begin
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3: begin
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if(b != 8'b0) begin
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if(b != 8'b0) begin
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i_z <= a/b;
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i_z <= a/b;
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end else begin
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end else begin
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i_z <= 16'b0;
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i_z <= 16'b0;
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i_flg <= 8'b10000;
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i_flg <= 8'b10000;
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end
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end
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end
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end
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// CMP
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// CMP
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4: begin
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4: begin
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/*
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/*
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Flag bits:
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Flag bits:
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000 -> No output
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000 -> No output
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001 -> a > b
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001 -> a > b
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010 -> a < b
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010 -> a < b
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011 -> No output
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011 -> No output
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100 -> a == b
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100 -> a == b
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101 -> a >= b
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101 -> a >= b
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110 -> a <= b
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110 -> a <= b
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111 -> No output
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111 -> No output
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*/
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*/
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i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 16'b0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 16'b1 : 16'b0;
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i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 16'b0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 16'b1 : 16'b0;
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i_flg <=
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i_flg <=
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(a > b ? 8'b100 : 8'b0) | // a > b
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(a > b ? 8'b100 : 8'b0) | // a > b
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(a == b ? 8'b1000 : 8'b0); // a == b
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(a == b ? 8'b1000 : 8'b0); // a == b
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end
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end
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// AND
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// AND
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5: begin
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5: begin
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i_z <= a & b;
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i_z <= a & b;
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// OR
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// OR
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6: begin
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6: begin
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i_z <= a | b;
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i_z <= a | b;
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// XOR
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// XOR
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7: begin
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7: begin
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i_z <= a ^ b;
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i_z <= a ^ b;
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// NOT
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// NOT
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8: begin
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8: begin
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i_z <= ~a;
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i_z <= ~a;
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// NAND
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// NAND
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9: begin
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9: begin
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i_z <= ~(a & b);
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i_z <= ~(a & b);
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// NOR
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// NOR
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10: begin
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10: begin
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i_z <= ~(a | b);
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i_z <= ~(a | b);
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// XNOR
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// XNOR
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11: begin
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11: begin
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i_z <= ~(a ^ b);
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i_z <= ~(a ^ b);
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i_flg <= 8'b0;
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i_flg <= 8'b0;
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end
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end
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// CL_MUL
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// CL_MUL
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12: begin
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12: begin
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i_z <=
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i_z <=
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(a[7] ? b << 7 : 16'b0) ^
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(a[7] ? b << 7 : 16'b0) ^
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(a[6] ? b << 6 : 16'b0) ^
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(a[6] ? b << 6 : 16'b0) ^
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(a[5] ? b << 5 : 16'b0) ^
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(a[5] ? b << 5 : 16'b0) ^
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(a[4] ? b << 4 : 16'b0) ^
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(a[4] ? b << 4 : 16'b0) ^
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(a[3] ? b << 3 : 16'b0) ^
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(a[3] ? b << 3 : 16'b0) ^
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(a[2] ? b << 2 : 16'b0) ^
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(a[2] ? b << 2 : 16'b0) ^
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(a[1] ? b << 1 : 16'b0) ^
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(a[1] ? b << 1 : 16'b0) ^
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(a[0] ? b : 16'b0);
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(a[0] ? b : 16'b0);
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i_flg <=
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i_flg <=
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(a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[6] && (b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[6] && (b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[5] && (b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[5] && (b[3] || b[4] || b[5] || b[6] || b[7])) ||
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(a[4] && (b[4] || b[5] || b[6] || b[7])) ||
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(a[4] && (b[4] || b[5] || b[6] || b[7])) ||
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(a[3] && (b[5] || b[6] || b[7])) ||
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(a[3] && (b[5] || b[6] || b[7])) ||
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(a[2] && (b[6] || b[7])) ||
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(a[2] && (b[6] || b[7])) ||
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(a[1] && b[7])
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(a[1] && b[7])
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? 8'b1 : 8'b0;
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? 8'b1 : 8'b0;
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end
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end
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default: begin
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i_z <= 16'b0;
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// SHR (flag: rotate)
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i_flg <= 8'b100000; // Unknown opcode
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13: begin
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end
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shift_rotate <= op[5];
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endcase
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i_z <= b >= 8 ? 16'b0 : rshift[2];
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i_flg <= rshift_underflow[0] || rshift_underflow[1] || rshift_underflow[2] || (b >= 8) ? 8'b10: 8'b0;
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end
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// SHL (flag: rotate)
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14: begin
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shift_rotate <= op[5];
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i_z <= b >= 8 ? 16'b0 : lshift[2];
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i_flg <= lshift_overflow[0] || lshift_overflow[1] || lshift_overflow[2] || (b >= 8) ? 8'b1 : 8'b0;
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end
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default: begin
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i_z <= 16'b0;
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i_flg <= 8'b100000; // Unknown opcode
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end
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endcase
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end
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end
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endmodule
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endmodule
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// Bit shifters
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module LeftBitShifter(
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input wire [bits-1:0] data,
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input wire doshift,
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input wire rotate,
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output wire [bits-1:0] out,
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output wire overflow
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);
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parameter bits;
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parameter shiftby;
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assign overflow = doshift && data[bits-1:shiftby] ? 1'b1 : 1'b0;
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assign out = doshift ? {data[bits-1-shiftby:0], rotate ? data[bits-1:bits-shiftby] : {shiftby{1'b0}}} : data;
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endmodule
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module RightBitShifter(
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input wire [bits-1:0] data,
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input wire doshift,
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input wire rotate,
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output wire [bits-1:0] out,
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output wire underflow
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);
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parameter bits;
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parameter shiftby;
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assign underflow = doshift && data[shiftby:0] ? 1'b1 : 1'b0;
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assign out = doshift ? {rotate ? data[shiftby-1:0] : {shiftby{1'b0}}, data[bits-1:shiftby]} : data;
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endmodule
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24
Callback.v
Normal file
24
Callback.v
Normal file
@ -0,0 +1,24 @@
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module Callback(
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input wire clk,
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input wire [ISIZE-1:0] countdown,
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input wire reset,
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output wire callback
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);
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parameter ISIZE;
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reg [ISIZE-1:0] counter;
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reg [1:0] ctr_trigger = 2'b10;
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assign callback = !counter & ctr_trigger;
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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counter <= countdown;
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ctr_trigger <= 2'b10;
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end
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else if(counter) counter <= counter - 1'b1;
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else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b01; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
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end
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endmodule
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21
RAM.v
21
RAM.v
@ -25,22 +25,21 @@ assign RAM_clk_enable = read_init != 3'b000;
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assign RAM_clk = clk; // RAM clock tracks processor input clock
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assign RAM_clk = clk; // RAM clock tracks processor input clock
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always @(posedge clk) begin
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always @(posedge clk or posedge read_rq) begin
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if(read_init) begin
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if(read_rq) begin
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read_init <= read_init + 3'b001;
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if(!read_init && !write_rq) begin
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RAM_state <= 4'b0001; // STATE: read
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read_init <= 3'b001;
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end
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end
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end
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always @(posedge read_rq) begin
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if(!read_init && !write_rq) begin
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read_init <= 3'b001;
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end
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end
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else if(read_init) begin
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read_init <= read_init + 3'b001;
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RAM_state <= 4'b0001; // STATE: read
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end
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end
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end
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always @(posedge write_rq) begin
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always @(posedge write_rq) begin
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if(!read_init && !read_rq) begin
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if(!read_init && !read_rq) begin
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//TODO: Implement read
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//TODO: Implement read
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end
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end
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end
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end
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@ -24,7 +24,8 @@ module SevenSegment(
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);
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);
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// ---- SETTINGS ---- //
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// ---- SETTINGS ---- //
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localparam PLL_SELECT = 3; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
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localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
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localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!!
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// ---- REGISTERS ---- //
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// ---- REGISTERS ---- //
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reg debounce; // Input debouncer
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reg debounce; // Input debouncer
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@ -42,6 +43,12 @@ wire [7:0] alu_out; // ALU (core0) output
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wire [7:0] alu_flags; // ALU (core0) output flags
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wire [7:0] alu_flags; // ALU (core0) output flags
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wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
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wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
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wire vga_clk; // VGA data clock
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wire vga_clk; // VGA data clock
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wire cb; // Callback/timeout
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wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to
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wire ram_request_read; // Trigger a read operation from main memory
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wire ram_request_write; // Trigger a write operation from main memory
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wire ram_event; // Event trigger from ram when an operation is completed (ex. a read op is ready)
|
||||||
|
wire [3:0] ram_state; // Main memory event information
|
||||||
|
|
||||||
// ---- WIRE ASSIGNS ---- //
|
// ---- WIRE ASSIGNS ---- //
|
||||||
assign pll[4] = clk;
|
assign pll[4] = clk;
|
||||||
@ -68,12 +75,39 @@ SegmentManager seg_display(
|
|||||||
.segments (seg_write)
|
.segments (seg_write)
|
||||||
);
|
);
|
||||||
|
|
||||||
VGA screen(clk, gfx_rgb, vga_clk, VGA_rgb, VGA_hsync, VGA_vsync);
|
// Graphics controller
|
||||||
|
VGA screen(clk, gfx_rgb, vga_clk, vga_coords[0], vga_coords[1], VGA_rgb, VGA_hsync, VGA_vsync);
|
||||||
|
|
||||||
|
// Arithmetic logic unit
|
||||||
ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
|
ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
|
||||||
|
|
||||||
|
// Clock generator
|
||||||
altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
|
altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
|
||||||
|
|
||||||
always @(posedge vga_clk) gfx_rgb <= alu_a[2:0];
|
// Callback module (generate timeouts) (Precision: 1/400M = 2.5ns)
|
||||||
|
Callback #(.ISIZE(32)) timeout(pll[3], 32'd400000000, ~value, cb);
|
||||||
|
|
||||||
|
// RAM module
|
||||||
|
RAM main_memory(
|
||||||
|
pll[RAM_PLL],
|
||||||
|
RAM_addr,
|
||||||
|
RAM_A10,
|
||||||
|
RAM_bank_sel,
|
||||||
|
RAM_data,
|
||||||
|
RAM_clk,
|
||||||
|
RAM_clk_enable,
|
||||||
|
RAM_enable,
|
||||||
|
RAM_strobe_col,
|
||||||
|
RAM_strobe_row,
|
||||||
|
RAM_write_enable,
|
||||||
|
ram_request_read,
|
||||||
|
ram_request_write,
|
||||||
|
ram_state,
|
||||||
|
ram_event
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge cb or negedge value) select_out <= cb ? 4'b0000 : 4'b1111;
|
||||||
|
always @(posedge vga_clk) gfx_rgb <= alu_a[2:0];
|
||||||
always @(posedge pll[PLL_SELECT]) begin
|
always @(posedge pll[PLL_SELECT]) begin
|
||||||
if(!latch && write && next) begin
|
if(!latch && write && next) begin
|
||||||
debounce <= 1'b1;
|
debounce <= 1'b1;
|
||||||
@ -137,9 +171,9 @@ always @(posedge pll[PLL_SELECT]) begin
|
|||||||
seg_buf_numbers[3] <= alu_flags[3:0];
|
seg_buf_numbers[3] <= alu_flags[3:0];
|
||||||
end
|
end
|
||||||
|
|
||||||
select_out[0] <= ~debounce;
|
//select_out[0] <= ~debounce;
|
||||||
select_out[1] <= write;
|
//select_out[1] <= write;
|
||||||
select_out[2] <= next;
|
//select_out[2] <= next;
|
||||||
select_out[3] <= latch;
|
//select_out[3] <= latch;
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
4
VGA.v
4
VGA.v
@ -2,6 +2,8 @@ module VGA(
|
|||||||
input wire clk,
|
input wire clk,
|
||||||
input wire [2:0] rgb_data,
|
input wire [2:0] rgb_data,
|
||||||
output reg graphics_clk,
|
output reg graphics_clk,
|
||||||
|
output wire [9:0] graphics_coords_x,
|
||||||
|
output wire [9:0] graphics_coords_y,
|
||||||
output wire [2:0] VGA_rgb,
|
output wire [2:0] VGA_rgb,
|
||||||
output wire VGA_hsync,
|
output wire VGA_hsync,
|
||||||
output wire VGA_vsync
|
output wire VGA_vsync
|
||||||
@ -27,6 +29,8 @@ wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vd
|
|||||||
assign VGA_hsync = (hcount > hsync_end);
|
assign VGA_hsync = (hcount > hsync_end);
|
||||||
assign VGA_vsync = (vcount > vsync_end);
|
assign VGA_vsync = (vcount > vsync_end);
|
||||||
assign VGA_rgb = (dat_act) ? rgb_data : 3'b0;
|
assign VGA_rgb = (dat_act) ? rgb_data : 3'b0;
|
||||||
|
assign graphics_coords_x = vcount;
|
||||||
|
assign graphics_coords_y = hcount;
|
||||||
|
|
||||||
// Clock divider
|
// Clock divider
|
||||||
always @(posedge clk) graphics_clk = ~graphics_clk;
|
always @(posedge clk) graphics_clk = ~graphics_clk;
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user