Added CLA adder circuit generator

FastAdder.py

@@ -0,0 +1 @@
+print((lambda count_i, gen: "\nmodule FastAdder"+str(count_i)+"(\n\tinput wire cin,\n\tinput wire ["+str(count_i-1)+":0] a,\n\t"+"input wire ["+str(count_i-1)+":0] b,\n\toutput wire ["+str(count_i-1)+":0] out,\n\toutput wire cout\n);\nwire ["+str(count_i-1)+":0] g = a & b;\nwire ["+str(count_i-1)+":0] p = a ^ b;\nassign out = a ^ b ^ {\n\t"+('\n\t'.join([gen(i) for i in range(count_i-2, -2, -1)]).replace("(cin),", "(cin)"))+"\n};\nassign cout = "+gen(count_i-1)[0:-1]+";\nendmodule\n")(int(input("Adder bit width: ")), lambda depth: ("("+(''.join([''.join([" p["+str(j)+"] &" for j in range(depth, i, -1)]) + (" g["+str(i)+"]) | (" if i >= 0 else "") for i in range(depth, -2, -1)]))+" cin),").replace("( ", "(")))

FastAdder.v

@@ -19,19 +19,38 @@ assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3]
 endmodule
 
 module FastAdder8(
-	input wire [WIRE_SIZE-1:0] a,
-	input wire [WIRE_SIZE-1:0] b,
-	output wire [WIRE_SIZE-1:0] out,
+	input wire c_in,
+	input wire [7:0] a,
+	input wire [7:0] b,
+	output wire [7:0] out,
 	output wire c_out
 );
 
-parameter WIRE_SIZE;
+wire [7:0] gen = a & b; // Generator
+wire [7:0] prp = a ^ b;	// Propogator
 
-genvar i;
-generate
-	for(i=0; i<WIRE_SIZE; i = i + 1) begin
-		
-	end
-endgenerate
+assign out = a ^ b ^ {
+	gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in),	// Carry 2
+	gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in),													// Carry 1
+	gen[0] | (prp[0] & c_in),																							// Carry 0
+	c_in																														// Carry -1 (in)
+};
+assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
 
 endmodule
+
+module FastAdder2(
+        input wire cin,
+        input wire [1:0] a,
+        input wire [1:0] b,
+        output wire [1:0] out,
+        output wire cout
+);
+wire [1:0] g = a & b;
+wire [1:0] p = a ^ b;
+assign out = a ^ b ^ {
+        (g[0]) | (p[0] & cin),
+        (cin)
+};
+assign cout = (g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin);
+endmodule

SevenSegment.v

@@ -25,18 +25,18 @@ localparam PLL_SELECT = 4; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50M
 
 // ----    REGISTERS   ---- //
 reg debounce;							// Input debouncer
-reg db_trap;
+reg db_trap;							// Debounce buffer
 reg [3:0] seg_buf_numbers [0:3];	// 7-segment binary-number-representation buffer
 reg [1:0] stage;						// Computational stage
-reg [7:0] alu_a;
-reg [7:0] alu_b;
-reg [7:0] alu_op;
+reg [7:0] alu_a;						// ALU (core0) input a
+reg [7:0] alu_b;						// ALU (core0) input b
+reg [7:0] alu_op;						// ALU (core0) opcode
 
 // ----     WIRES      ---- //
 wire [7:0] seg_buf[0:3];			// Encoded segment buffer (8-bit expanded 4-bit number buffer)
-wire [7:0] alu_out;
-wire [7:0] alu_flags;
-wire [4:0] pll;
+wire [7:0] alu_out;					// ALU (core0) output
+wire [7:0] alu_flags;				// ALU (core0) output flags
+wire [4:0] pll;						// Phase-locked-loop connections (+ source clock)
 
 assign pll[4] = clk;
 
@@ -47,6 +47,7 @@ initial seg_buf_numbers[1] = 4'b0000;
 initial seg_buf_numbers[2] = 4'b0000;
 initial seg_buf_numbers[3] = 4'b0000;
 initial debounce = 0;
+initial db_trap = 1;
 
 // Hex encoders for each 4-bit input set. Generates an 8-bit hex output
 SegmentHexEncoder enc0(.number (seg_buf_numbers[0]), .encoded (seg_buf[0]));