Added basic VGA graphics support
Generated some basic FastAdders Generalized FastAdder to include all fast math modules Other minor changes
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@ -24,3 +24,4 @@ incremental_db/*
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*.qws
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*.qsf
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*.qpf
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.sopc_builder/*
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60
ALU.v
60
ALU.v
@ -25,15 +25,19 @@ H: N/A
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reg [15:0] i_z;
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reg [7:0] i_flg;
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wire [8:0] add_out;
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assign z = i_z[7:0];
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assign o_flags = i_flg;
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FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[7:0]), .cout(add_out[8]));
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always @* begin
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case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
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// ADD
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0: begin
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i_z <= a+b;
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i_flg <= z < a ? 1 : 0; // Set overflow flag if necessary
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i_z <= add_out;
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i_flg <= add_out[8] ? 8'b1 : 8'b0; // Set overflow flag if necessary
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end
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// SUB
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@ -45,17 +49,17 @@ always @* begin
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// MUL
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2: begin
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i_z <= a*b;
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i_flg <= i_z[15:8] != 8'b00000000 ? 1 : 0;
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i_flg <= i_z[15:8] != 8'b0 ? 8'b1 : 8'b0;
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end
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// DIV
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3: begin
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if(b != 8'b00000000) begin
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if(b != 8'b0) begin
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i_z <= a/b;
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end else begin
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i_z <= 8'b00000000;
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i_flg <= 8'b00010000;
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i_z <= 16'b0;
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i_flg <= 8'b10000;
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end
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end
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@ -74,65 +78,65 @@ always @* begin
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111 -> No output
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*/
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i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 1 : 0;
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i_z <= (op[7:5] == 3'b000) || (op[7:5] == 3'b011) || (op[7:5] == 3'b111) ? 16'b0 : (op[5] && a > b) || (op[6] && a < b ) || (op[7] && a == b) ? 16'b1 : 16'b0;
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i_flg <=
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(a > b ? 4 : 0) | // a > b
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(a == b ? 8 : 0); // a == b
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(a > b ? 8'b100 : 8'b0) | // a > b
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(a == b ? 8'b1000 : 8'b0); // a == b
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end
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// AND
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5: begin
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i_z <= a & b;
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// OR
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6: begin
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i_z <= a | b;
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// XOR
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7: begin
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i_z <= a ^ b;
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// NOT
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8: begin
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i_z <= ~a;
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// NAND
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9: begin
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i_z <= ~(a & b);
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// NOR
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10: begin
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i_z <= ~(a | b);
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// XNOR
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11: begin
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i_z <= ~(a ^ b);
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i_flg <= 8'b00000000;
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i_flg <= 8'b0;
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end
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// CL_MUL
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12: begin
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i_z <=
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(a[7] ? b << 7 : 0) ^
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(a[6] ? b << 6 : 0) ^
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(a[5] ? b << 5 : 0) ^
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(a[4] ? b << 4 : 0) ^
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(a[3] ? b << 3 : 0) ^
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(a[2] ? b << 2 : 0) ^
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(a[1] ? b << 1 : 0) ^
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(a[0] ? b : 0);
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(a[7] ? b << 7 : 16'b0) ^
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(a[6] ? b << 6 : 16'b0) ^
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(a[5] ? b << 5 : 16'b0) ^
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(a[4] ? b << 4 : 16'b0) ^
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(a[3] ? b << 3 : 16'b0) ^
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(a[2] ? b << 2 : 16'b0) ^
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(a[1] ? b << 1 : 16'b0) ^
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(a[0] ? b : 16'b0);
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i_flg <=
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(a[7] && (b[1] || b[2] || b[3] || b[4] || b[5] || b[6] || b[7])) ||
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@ -142,11 +146,11 @@ always @* begin
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(a[3] && (b[5] || b[6] || b[7])) ||
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(a[2] && (b[6] || b[7])) ||
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(a[1] && b[7])
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? 1 : 0;
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? 8'b1 : 8'b0;
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end
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default: begin
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i_z <= 0;
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i_flg <= 32; // Unknown opcode
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i_z <= 16'b0;
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i_flg <= 8'b100000; // Unknown opcode
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end
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endcase
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end
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@ -16,11 +16,11 @@ assign divided = div_int; // Assign internal result state to external output
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// Division
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always @ (posedge clk) begin
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if(div == divideby) begin
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div_int <= pulsemode ? 1 : ~div_int;
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div_int <= pulsemode ? 1'b1 : ~div_int;
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div <= 0;
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end else begin
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if(pulsemode) div_int <= 0;
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div <= div + 1;
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div <= div + 1'b1;
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end
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end
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56
FastAdder.v
56
FastAdder.v
@ -1,56 +0,0 @@
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module FastAdder4(
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input wire c_in,
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input wire [3:0] a,
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input wire [3:0] b,
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output wire [3:0] out,
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output wire c_out
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);
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wire [3:0] gen = a & b; // Generator
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wire [3:0] prp = a ^ b; // Propogator
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assign out = a ^ b ^ {
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gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in), // Carry 2
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gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in), // Carry 1
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gen[0] | (prp[0] & c_in), // Carry 0
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c_in // Carry -1 (in)
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};
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assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
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endmodule
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module FastAdder8(
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input wire c_in,
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input wire [7:0] a,
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input wire [7:0] b,
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output wire [7:0] out,
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output wire c_out
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);
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wire [7:0] gen = a & b; // Generator
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wire [7:0] prp = a ^ b; // Propogator
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assign out = a ^ b ^ {
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gen[2] | (prp[2] & gen[1]) | (prp[2] & prp[1] & gen[0]) | (prp[2] & prp[1] & prp[0] & c_in), // Carry 2
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gen[1] | (prp[1] & gen[0]) | (prp[1] & prp[0] & c_in), // Carry 1
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gen[0] | (prp[0] & c_in), // Carry 0
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c_in // Carry -1 (in)
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};
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assign c_out = gen[3] | (prp[3] & gen[2]) | (prp[3] & prp[2] & gen[1]) | (prp[3] & prp[2] & prp[1] & gen[0]) | (prp[3] & prp[2] & prp[1] & prp[0] & c_in);
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endmodule
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module FastAdder2(
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input wire cin,
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input wire [1:0] a,
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input wire [1:0] b,
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output wire [1:0] out,
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output wire cout
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);
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wire [1:0] g = a & b;
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wire [1:0] p = a ^ b;
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assign out = a ^ b ^ {
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(g[0]) | (p[0] & cin),
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(cin)
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};
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assign cout = (g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin);
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endmodule
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58
FastMath.v
Normal file
58
FastMath.v
Normal file
@ -0,0 +1,58 @@
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// 2-bit fast adder
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module FastAdder2(
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input wire cin,
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input wire [1:0] a,
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input wire [1:0] b,
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output wire [1:0] out,
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output wire cout
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);
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wire [1:0] g = a & b;
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wire [1:0] p = a ^ b;
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assign out = a ^ b ^ {
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(g[0]) | (p[0] & cin),
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(cin)
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};
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assign cout = (g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin);
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endmodule
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// 4-bit fast adder
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module FastAdder4(
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input wire cin,
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input wire [3:0] a,
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input wire [3:0] b,
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output wire [3:0] out,
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output wire cout
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);
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wire [3:0] g = a & b;
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wire [3:0] p = a ^ b;
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assign out = a ^ b ^ {
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(g[2]) | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin),
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(g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin),
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(g[0]) | (p[0] & cin),
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(cin)
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};
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assign cout = (g[3]) | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin);
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endmodule
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// 8-bit fast adder
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module FastAdder8(
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input wire cin,
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input wire [7:0] a,
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input wire [7:0] b,
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output wire [7:0] out,
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output wire cout
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);
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wire [7:0] g = a & b;
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wire [7:0] p = a ^ b;
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assign out = a ^ b ^ {
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(g[6]) | (p[6] & g[5]) | (p[6] & p[5] & g[4]) | (p[6] & p[5] & p[4] & g[3]) | (p[6] & p[5] & p[4] & p[3] & g[2]) | (p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin),
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(g[5]) | (p[5] & g[4]) | (p[5] & p[4] & g[3]) | (p[5] & p[4] & p[3] & g[2]) | (p[5] & p[4] & p[3] & p[2] & g[1]) | (p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin),
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(g[4]) | (p[4] & g[3]) | (p[4] & p[3] & g[2]) | (p[4] & p[3] & p[2] & g[1]) | (p[4] & p[3] & p[2] & p[1] & g[0]) | (p[4] & p[3] & p[2] & p[1] & p[0] & cin),
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(g[3]) | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin),
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(g[2]) | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin),
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(g[1]) | (p[1] & g[0]) | (p[1] & p[0] & cin),
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(g[0]) | (p[0] & cin),
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(cin)
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};
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assign cout = (g[7]) | (p[7] & g[6]) | (p[7] & p[6] & g[5]) | (p[7] & p[6] & p[5] & g[4]) | (p[7] & p[6] & p[5] & p[4] & g[3]) | (p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);
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endmodule
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@ -20,7 +20,7 @@ Divider #(.divideby(25000), .divide_reg_size(17)) divider_audio(clk, clk_graphic
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// Change the active segment data
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always @(posedge clk_graphics) begin
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segment_select <=(segment_select << 1) | segment_select[3];
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seg_sel_track <= seg_sel_track + 1;
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seg_sel_track <= seg_sel_track + 1'b1;
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end
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// Assign the active segment data to the segment bus
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@ -1,4 +1,4 @@
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module SevenSegment (
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module SevenSegment(
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input wire latch, // S4
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input wire next, // S2
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input wire value, // S3
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@ -9,7 +9,7 @@ module SevenSegment (
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output [7:0] seg_write, // a-g + dp [0-7] + 8
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output reg beep, // Buzzer
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output wire [10:0] RAM_addr, // RAM address buffer
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output wire RAM_A10,
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output wire RAM_A10, // RAM A10 precharge/address
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output wire [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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@ -17,11 +17,14 @@ module SevenSegment (
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output wire RAM_enable, // RAM chip enable
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output wire RAM_strobe_row, // RAM row strobe
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output wire RAM_strobe_col, // RAM column strobe
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output wire RAM_write_enable // RAM data bus write enable
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output wire RAM_write_enable, // RAM data bus write enable
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output wire VGA_vsync, // VGA display vsync trigger
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output wire VGA_hsync, // VGA display hsync trigger
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output wire [2:0] VGA_rgb // VGA color channels [0]: RED, [1]: GREEN, [2]: BLUE
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);
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// ---- SETTINGS ---- //
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localparam PLL_SELECT = 4; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
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localparam PLL_SELECT = 3; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
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// ---- REGISTERS ---- //
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reg debounce; // Input debouncer
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@ -31,23 +34,22 @@ reg [1:0] stage; // Computational stage
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reg [7:0] alu_a; // ALU (core0) input a
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reg [7:0] alu_b; // ALU (core0) input b
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reg [7:0] alu_op; // ALU (core0) opcode
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reg [2:0] gfx_rgb; // VGA color channels
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// ---- WIRES ---- //
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wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer)
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wire [7:0] alu_out; // ALU (core0) output
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wire [7:0] alu_flags; // ALU (core0) output flags
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wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
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wire vga_clk; // VGA data clock
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// ---- WIRE ASSIGNS ---- //
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assign pll[4] = clk;
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// ---- INITIAL VALUES ---- //
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initial select_out = 4'b1111;
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initial seg_buf_numbers[0] = 4'b0000;
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initial seg_buf_numbers[1] = 4'b0000;
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initial seg_buf_numbers[2] = 4'b0000;
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initial seg_buf_numbers[3] = 4'b0000;
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initial debounce = 0;
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initial db_trap = 1;
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initial debounce = 1'b0;
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initial db_trap = 1'b1;
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// Hex encoders for each 4-bit input set. Generates an 8-bit hex output
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SegmentHexEncoder enc0(.number (seg_buf_numbers[0]), .encoded (seg_buf[0]));
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@ -66,37 +68,41 @@ SegmentManager seg_display(
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.segments (seg_write)
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);
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VGA screen(clk, gfx_rgb, vga_clk, VGA_rgb, VGA_hsync, VGA_vsync);
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ALU core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
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altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
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always @(posedge vga_clk)
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gfx_rgb <= alu_a[2:0];
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always @(posedge pll[PLL_SELECT]) begin
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if(!latch && write && next) begin
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debounce <= 1;
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debounce <= 1'b1;
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end
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if(write && next && db_trap) begin
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debounce <= 0;
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db_trap <= 0;
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debounce <= 1'b0;
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db_trap <= 1'b0;
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end
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if(!write && debounce && !db_trap) begin
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db_trap <= 1;
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if(stage == 0) begin
|
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alu_a <= alu_a + 1;
|
||||
end else if(stage == 1) begin
|
||||
alu_b <= alu_b + 1;
|
||||
end else if(stage == 2) begin
|
||||
alu_op <= alu_op + 1;
|
||||
db_trap <= 1'b1;
|
||||
if(stage == 2'b0) begin
|
||||
alu_a <= alu_a + 8'b1;
|
||||
end else if(stage == 2'b1) begin
|
||||
alu_b <= alu_b + 8'b1;
|
||||
end else if(stage == 2'b10) begin
|
||||
alu_op <= alu_op + 8'b1;
|
||||
end
|
||||
end else if (!next && debounce && !db_trap) begin
|
||||
db_trap <= 1;
|
||||
stage <= stage + 1;
|
||||
db_trap <= 1'b1;
|
||||
stage <= stage + 2'b1;
|
||||
|
||||
if(stage == 2'b01) begin
|
||||
seg_buf_numbers[0] <= 0;
|
||||
seg_buf_numbers[1] <= 0;
|
||||
seg_buf_numbers[2] <= 0;
|
||||
seg_buf_numbers[3] <= 0;
|
||||
seg_buf_numbers[0] <= 4'b0;
|
||||
seg_buf_numbers[1] <= 4'b0;
|
||||
seg_buf_numbers[2] <= 4'b0;
|
||||
seg_buf_numbers[3] <= 4'b0;
|
||||
end
|
||||
else if(stage == 2'b10) begin
|
||||
seg_buf_numbers[0] <= alu_out[7:4];
|
||||
@ -105,13 +111,13 @@ always @(posedge pll[PLL_SELECT]) begin
|
||||
seg_buf_numbers[3] <= alu_flags[3:0];
|
||||
end
|
||||
else if(stage == 2'b11) begin
|
||||
seg_buf_numbers[0] <= alu_a[7:4];
|
||||
seg_buf_numbers[1] <= alu_a[3:0];
|
||||
seg_buf_numbers[2] <= alu_b[7:4];
|
||||
seg_buf_numbers[3] <= alu_b[3:0];
|
||||
alu_a <= 0;
|
||||
alu_b <= 0;
|
||||
alu_op <= 0;
|
||||
seg_buf_numbers[0] <= 4'b0;
|
||||
seg_buf_numbers[1] <= 4'b0;
|
||||
seg_buf_numbers[2] <= 4'b0;
|
||||
seg_buf_numbers[3] <= 4'b0;
|
||||
alu_a <= 8'b0;
|
||||
alu_b <= 8'b0;
|
||||
alu_op <= 8'b0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -123,8 +129,8 @@ always @(posedge pll[PLL_SELECT]) begin
|
||||
end else if(stage == 2'b10) begin
|
||||
seg_buf_numbers[0] <= alu_op[7:4];
|
||||
seg_buf_numbers[1] <= alu_op[3:0];
|
||||
seg_buf_numbers[2] <= 0;
|
||||
seg_buf_numbers[3] <= 0;
|
||||
seg_buf_numbers[2] <= 4'b0;
|
||||
seg_buf_numbers[3] <= 4'b0;
|
||||
end else if(stage == 2'b11) begin
|
||||
seg_buf_numbers[0] <= alu_out[7:4];
|
||||
seg_buf_numbers[1] <= alu_out[3:0];
|
||||
|
||||
41
VGA.v
Normal file
41
VGA.v
Normal file
@ -0,0 +1,41 @@
|
||||
module VGA(
|
||||
input wire clk,
|
||||
input wire [2:0] rgb_data,
|
||||
output reg graphics_clk,
|
||||
output wire [2:0] VGA_rgb,
|
||||
output wire VGA_hsync,
|
||||
output wire VGA_vsync
|
||||
);
|
||||
|
||||
parameter
|
||||
hsync_end = 10'd95,
|
||||
hdat_begin = 10'd143,
|
||||
hdat_end = 10'd783,
|
||||
hpixel_end = 10'd799,
|
||||
vsync_end = 10'd1,
|
||||
vdat_begin = 10'd34,
|
||||
vdat_end = 10'd514,
|
||||
vline_end = 10'd524;
|
||||
|
||||
reg [9:0] hcount;
|
||||
reg [9:0] vcount;
|
||||
|
||||
wire hcount_ov = (hcount == hpixel_end);
|
||||
wire vcount_ov = (vcount == vline_end);
|
||||
wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));
|
||||
|
||||
assign VGA_hsync = (hcount > hsync_end);
|
||||
assign VGA_vsync = (vcount > vsync_end);
|
||||
assign VGA_rgb = (dat_act) ? rgb_data : 3'b0;
|
||||
|
||||
// Clock divider
|
||||
always @(posedge clk) graphics_clk = ~graphics_clk;
|
||||
|
||||
// Graphics boundary calculation
|
||||
always @(posedge graphics_clk) begin
|
||||
if(hcount_ov && vcount_ov) vcount <= 10'b0;
|
||||
else if(hcount_ov) vcount <= vcount + 10'b1;
|
||||
if (hcount_ov) hcount <= 10'd0;
|
||||
else hcount <= hcount + 10'd1;
|
||||
end
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user