GabrielTofvesson
a3f7a48276
Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging
25 lines
552 B
Verilog
25 lines
552 B
Verilog
module Callback(
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input wire clk,
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input wire [ISIZE-1:0] countdown,
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input wire reset,
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output wire callback
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);
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parameter ISIZE;
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reg [ISIZE-1:0] counter;
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reg [2:0] ctr_trigger = 2'b00;
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assign callback = !counter && ctr_trigger ? 1'b1 : 1'b0;
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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counter <= countdown;
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ctr_trigger <= 2'b10;
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end
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else if(counter) counter <= counter - 1'b1;
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else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
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end
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endmodule
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