Fixed minor issues in ALU.v
Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging
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34
ALU.v
34
ALU.v
@ -31,9 +31,9 @@ reg shift_rotate;
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wire [BITS:0] add_out;
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wire [BITS-1:0] lshift [0:LOG2_BITS];
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wire [LOG2_BITS:0] lshift_overflow;
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wire [LOG2_BITS-1:0] lshift_overflow;
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wire [BITS-1:0] rshift [0:LOG2_BITS];
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wire [LOG2_BITS:0] rshift_underflow;
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wire [LOG2_BITS-1:0] rshift_underflow;
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assign z = i_z[7:0];
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assign o_flags = i_flg;
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@ -42,33 +42,13 @@ FastAdder8 fa8(.cin(), .a(a), .b(b), .out(add_out[BITS-1:0]), .cout(add_out[BITS
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genvar i;
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generate
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for(i = 1; i<LOG2_BITS; i = i + 1) begin : shifters
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LeftBitShifter #(.bits(BITS), .shiftby(2**(i-1))) lsh(i==1 ? a : lshift[i-1], b[i], shift_rotate, lshift[i], lshift_overflow[i]);
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RightBitShifter #(.bits(BITS), .shiftby(2**(i-1))) rsh(i==1 ? a : rshift[i-1], b[i], shift_rotate, rshift[i], rshift_underflow[i]);
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for(i = 0; i<LOG2_BITS; i = i + 1) begin : shifters
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LeftBitShifter #(.bits(BITS), .shiftby(2**i)) lsh(i==0 ? a : lshift[i-1], b[i], shift_rotate, lshift[i], lshift_overflow[i]);
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RightBitShifter #(.bits(BITS), .shiftby(2**i)) rsh(i==0 ? a : rshift[i-1], b[i], shift_rotate, rshift[i], rshift_underflow[i]);
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end
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endgenerate
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integer j;
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// Left shift decoder
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//LeftBitShifter #(.bits(BITS), .shiftby(1)) (a, b[0], shift_rotate, lshift[0], lshift_overflow[0]);
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//LeftBitShifter #(.bits(BITS), .shiftby(2)) (lshift[0], b[1], shift_rotate, lshift[1], lshift_overflow[1]);
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//LeftBitShifter #(.bits(BITS), .shiftby(4)) (lshift[1], b[2], shift_rotate, lshift[2], lshift_overflow[2]);
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//LeftBitShifter #(.bits(8), .shiftby(8)) (lshift[2], b[3], lshift[3], lshift_overflow[3]);
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//LeftBitShifter #(.bits(8), .shiftby(16)) (lshift[3], b[4], lshift[4], lshift_overflow[4]);
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//LeftBitShifter #(.bits(8), .shiftby(32)) (lshift[4], b[5], lshift[5], lshift_overflow[5]);
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//LeftBitShifter #(.bits(8), .shiftby(64)) (lshift[5], b[6], lshift[6], lshift_overflow[6]);
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//LeftBitShifter #(.bits(8), .shiftby(128)) (lshift[6], b[7], lshift[7], lshift_overflow[7]);
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// Right shift decoder
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//RightBitShifter #(.bits(BITS), .shiftby(1)) (a, b[0], shift_rotate, rshift[0], rshift_underflow[0]);
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//RightBitShifter #(.bits(BITS), .shiftby(2)) (rshift[0], b[1], shift_rotate, rshift[1], rshift_underflow[1]);
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//RightBitShifter #(.bits(BITS), .shiftby(4)) (rshift[1], b[2], shift_rotate, rshift[2], rshift_underflow[2]);
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//RightBitShifter #(.bits(8), .shiftby(8)) (rshift[2], b[3], rshift[3], rshift_underflow[3]);
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//RightBitShifter #(.bits(8), .shiftby(16)) (rshift[3], b[4], rshift[4], rshift_underflow[4]);
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//RightBitShifter #(.bits(8), .shiftby(32)) (rshift[4], b[5], rshift[5], rshift_underflow[5]);
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//RightBitShifter #(.bits(8), .shiftby(64)) (rshift[5], b[6], rshift[6], rshift_underflow[6]);
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//RightBitShifter #(.bits(8), .shiftby(128)) (rshift[6], b[7], rshift[7], rshift_underflow[7]);
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integer j, k;
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always @* begin
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case(op & 8'b00011111) // 5-bit instructions: 3 flag bits
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@ -163,7 +143,7 @@ always @* begin
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i_z <= ~(a ^ b);
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i_flg <= 8'b0;
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end
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// CL_MUL
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/*
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12: begin
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@ -8,9 +8,9 @@ module Callback(
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parameter ISIZE;
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reg [ISIZE-1:0] counter;
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reg [2:0] ctr_trigger = 2'b10;
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reg [2:0] ctr_trigger = 2'b00;
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assign callback = !counter & ctr_trigger;
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assign callback = !counter && ctr_trigger ? 1'b1 : 1'b0;
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always @(posedge clk or posedge reset) begin
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if(reset) begin
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227
RAM.v
227
RAM.v
@ -1,69 +1,188 @@
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/*
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* DEVICE INFORMATION:
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* HY57V641620FTP-7:
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* RAS latency: 2 or 3 cycles
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* RCD latency: 2 or 3 cycles
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* full address_select available for row selection
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* address_select[7:0] available for col selection
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*/
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module RAM(
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input wire clk,
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output wire [10:0] RAM_addr, // RAM address buffer
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output wire RAM_A10, // RAM address/auto-precharge
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output wire [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output wire RAM_enable, // RAM chip enable
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output wire RAM_strobe_row, // RAM row strobe
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output wire RAM_strobe_col, // RAM column strobe
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output wire RAM_write_enable, // RAM data bus write enable
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input wire read_rq, // Read request (Internal)
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input wire write_rq, // Write request (Internal)
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input wire [1:0] access_bank, // Which bank to access
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output reg [15:0] RAM_state, // State information (Internal)
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output wire [3:0] op_trigger // Event trigger wire (per bank)
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input wire clk, // Clock signal
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output reg [10:0] RAM_addr, // RAM address buffer
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output reg RAM_A10, // RAM address/auto-precharge
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output reg [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output reg RAM_enable, // RAM chip enable
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output reg RAM_strobe_row, // RAM row strobe
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output reg RAM_strobe_col, // RAM column strobe
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output reg RAM_write_enable, // RAM data bus write enable
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input wire read_rq, // Read request (Internal)
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input wire write_rq, // Write request (Internal)
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input wire [1:0] access_bank, // Which bank to access
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output wire op_trigger, // Event trigger wire
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input wire [11:0] address_select, // Address selection when accessing RAM,
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input wire stop_access, // Close a row
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output reg [1:0] op_bank // Bank being accessed when op_trigger is pulled high
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);
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reg [2:0] read_init[0:3]; // Whether or not a read operation has been initiated
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reg trigger_low; // If trigger should be pulled low on next clock cycle
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parameter CPB = 4; // Specifies in bit length how many cycles a bank burst can allocate for itself before other banks are checked
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parameter tRCD = 3 + 1; // Assume RCD latency of 3 cycles
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parameter tRAS = 3 + 1; // Assume CAS latency of 3 cycles
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genvar k;
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reg [CPB-1:0] acc_cycles; // Cycles used on current bank
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reg [1:0] acc_bank; // Which bank is allocating read cycles
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reg [1:0] acc_close[0:3]; // Requests a close of the current row
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reg [3:0] acc_type; // The current access type of the bank (0: READ, 1: WRITE)
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reg [3:0] acc_state [0:3]; // Current access state for each bank (0: READY, 1: OPENING, 2: tRCD, 3: READ, 4: STOPPING)
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reg [3:0] acc_init_callback; // Pull this high to initiate a callback
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reg [1:0] event_trigger; // Event triggers drive op_trigger
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wire [3:0] acc_event; // Event update callback wire
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wire [2:0] callback_timeout[0:3]; // Callback clock cycle definition
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Callback #(.ISIZE(3)) cb0(clk, callback_timeout[0], acc_init_callback[0], acc_event[0]);
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Callback #(.ISIZE(3)) cb1(clk, callback_timeout[1], acc_init_callback[1], acc_event[1]);
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Callback #(.ISIZE(3)) cb2(clk, callback_timeout[2], acc_init_callback[2], acc_event[2]);
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Callback #(.ISIZE(3)) cb3(clk, callback_timeout[3], acc_init_callback[3], acc_event[3]);
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// Initialize the ram in an inactive state
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initial RAM_enable = 1'b1;
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initial RAM_strobe_row = 1'b1;
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initial RAM_strobe_col = 1'b1;
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initial RAM_write_enable = 1'b1;
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initial acc_bank = 1'b1;
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assign op_trigger = event_trigger[0] ^ event_trigger[1];
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assign RAM_clk = clk;
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assign RAM_clk_enable = (acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]) ? 1'b1 : 1'b0;
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genvar n;
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generate
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for(k = 0; k<4; k = k + 1) begin : trigger_gen
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assign op_trigger[k] = read_init[k] == 3'b011;
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end
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for(n = 0; n < 4; n = n + 1) begin : gen_callback_timing
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assign callback_timeout[n] = acc_state[n][1] ? tRAS : tRCD;
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end
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endgenerate
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assign RAM_enable = read_init[0] == 3'b000 && read_init[1] == 3'b000 && read_init[2] == 3'b000 && read_init[3] == 3'b000;
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assign RAM_clk_enable = read_init[0] != 3'b000 && read_init[1] != 3'b000 && read_init[2] != 3'b000 && read_init[3] != 3'b000;
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assign RAM_clk = clk; // RAM clock tracks processor input clock
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integer i;
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always @(posedge clk or posedge read_rq) begin
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if(read_rq) begin
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if(!read_init[access_bank] && !write_rq) begin
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read_init[access_bank] <= 3'b001;
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end
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always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge stop_access or posedge clk) begin
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if(read_rq || write_rq) begin
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if(acc_state[access_bank] == 4'b0000) begin
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RAM_enable <= 1'b0;
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RAM_strobe_row <= 1'b0;
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RAM_strobe_col <= 1'b1;
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RAM_write_enable <= 1'b1;
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RAM_bank_sel <= access_bank;
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RAM_addr <= {address_select[11], address_select[9:0]};
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RAM_A10 <= address_select[10];
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acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1;
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acc_state[access_bank] <= 4'b0001;
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acc_init_callback[access_bank] <= 1'b1;
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acc_close[access_bank] <= 1'b0;
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end
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end
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else begin
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if(read_init[0]) begin
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read_init[0] <= read_init[0] + 3'b001; // Increment read
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RAM_state[3:0] <= 4'b0001; // STATE: read
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end
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if(read_init[1]) begin
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read_init[1] <= read_init[1] + 3'b001; // Increment read
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RAM_state[7:4] <= 4'b0001; // STATE: read
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end
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if(read_init[2]) begin
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read_init[2] <= read_init[2] + 3'b001; // Increment read
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RAM_state[11:8] <= 4'b0001; // STATE: read
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end
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if(read_init[3]) begin
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read_init[3] <= read_init[3] + 3'b001; // Increment read
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RAM_state[15:12] <= 4'b0001; // STATE: read
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end
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else if(stop_access) begin
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if(acc_state[access_bank])
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acc_close[access_bank] <= 1'b1;
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end
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else if(clk) begin
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for(i = 0; i < 4; i = i + 1)
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if(acc_state[i] == 4'b0010)
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acc_init_callback[i] <= 1'b1;
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if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]))
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RAM_enable <= 1'b1;
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// Bank access management
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acc_cycles[acc_bank] <= acc_cycles[acc_bank] + 1'b1;
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if(acc_cycles[acc_bank] == {CPB{1'b1}}) begin
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// Close banks as needed
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if(acc_close[0]) begin
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acc_close[0] <= 1'b0;
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RAM_bank_sel <= 2'b00;
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acc_state[0] <= 4'b0000;
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end
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else if(acc_close[1]) begin
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acc_close[1] <= 1'b0;
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RAM_bank_sel <= 2'b01;
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acc_state[1] <= 4'b0000;
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end
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else if(acc_close[2]) begin
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acc_close[2] <= 1'b0;
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RAM_bank_sel <= 2'b10;
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acc_state[2] <= 4'b0000;
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end
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else if(acc_close[3]) begin
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acc_close[3] <= 1'b0;
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RAM_bank_sel <= 2'b11;
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acc_state[3] <= 4'b0000;
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end
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// Increment bank tracker
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if(~(acc_close[0] | acc_close[1] | acc_close[2] | acc_close[3])) begin
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acc_bank <= acc_bank + 1;
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acc_cycles <= {CPB{1'b0}};
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end
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else begin
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// Trigger RAM row-close event
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RAM_enable <= 1'b0;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b1;
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RAM_write_enable <= 1'b0;
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end
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end
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else begin
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// Access bank
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for(i = 0; i < 4; i = i + 1) begin
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// Bank_{i} active and not closing and...
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// Enough cycles left or when no other bank is active or...
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// Bank_{i+1} at cycle limit and next banks inactive or bank is closing or...
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// Bank_{i+2} at cycle limit and next bank inactive or bank is closing or...
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// Bank_{i+3} at cycle limit or closing
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if(!acc_close[i] && acc_state[i] == 4'b0100 && (
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(acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 4'b0100 && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100))) ||
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(acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100)) ||
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(acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 4'b0100)) ||
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(acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}}))
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)) begin
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RAM_bank_sel <= i;
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RAM_addr <= {2'b0, RAM_addr[7:0]};
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RAM_A10 <= 1'b1;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b0;
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RAM_write_enable <= ~acc_type[i];
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op_bank <= i;
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event_trigger[0] <= event_trigger[1] ? 1'b0 : 1'b1;
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end
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end
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end
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end
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else if(acc_event) begin
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for(i = 0; i < 4; i = i + 1) begin
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if(acc_state[i] == 4'b0001) begin
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RAM_bank_sel <= i;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b0;
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RAM_write_enable <= ~acc_type[i];
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RAM_A10 <= 1;
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acc_state[i] <= 4'b0010;
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acc_init_callback[i] <= 1'b0;
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end
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else if(acc_state[i] == 4'b0010) begin
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acc_init_callback[i] <= 1'b0;
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acc_state[i] <= 4'b0100;
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end
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end
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end
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end
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always @(posedge write_rq) begin
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if(!read_init[access_bank] && !read_rq) begin
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//TODO: Implement read
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end
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end
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// Reset op_trigger by tracking posedge-driven event_trigger
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always @(negedge clk) event_trigger[1] <= event_trigger[0] ? 1'b1 : 1'b0;
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endmodule
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@ -28,15 +28,17 @@ localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz,
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localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!!
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// ---- REGISTERS ---- //
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reg debounce; // Input debouncer
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reg db_trap; // Debounce buffer
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reg [3:0] seg_buf_numbers [0:3]; // 7-segment binary-number-representation buffer
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reg [1:0] stage; // Computational stage
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reg [7:0] alu_a; // ALU (core0) input a
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reg [7:0] alu_b; // ALU (core0) input b
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reg [7:0] alu_op; // ALU (core0) opcode
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reg [2:0] gfx_rgb; // VGA color channels
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reg [1:0] ram_bank_sel; // Which ram bank to access
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reg debounce; // Input debouncer
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reg db_trap; // Debounce buffer
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reg [3:0] seg_buf_numbers [0:3];// 7-segment binary-number-representation buffer
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reg [1:0] stage; // Computational stage
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reg [7:0] alu_a; // ALU (core0) input a
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reg [7:0] alu_b; // ALU (core0) input b
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reg [7:0] alu_op; // ALU (core0) opcode
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reg [2:0] gfx_rgb; // VGA color channels
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reg [1:0] ram_bank_sel; // Which ram bank to access
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reg [11:0] ram_addr; // RAM address selection
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reg ram_close; // RAM close-row trigger
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// ---- WIRES ---- //
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wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer)
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@ -48,8 +50,8 @@ wire cb; // Callback/timeout
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wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to
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wire ram_request_read; // Trigger a read operation from main memory
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wire ram_request_write; // Trigger a write operation from main memory
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wire [3:0] ram_event; // Event trigger from ram when an operation is completed (ex. a read op is ready)
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wire [15:0] ram_state; // Main memory event information (0:3; bank0, 4:7; bank1, 8:11; bank2, 12:15; bank3)
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wire ram_event; // Event trigger from ram when a r/w operation is ready
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wire [1:0] ram_event_bank; // Which bank an event is happening on
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// ---- WIRE ASSIGNS ---- //
|
||||
assign pll[4] = clk;
|
||||
@ -104,8 +106,10 @@ RAM main_memory(
|
||||
ram_request_read,
|
||||
ram_request_write,
|
||||
ram_bank_sel,
|
||||
ram_state,
|
||||
ram_event
|
||||
ram_event,
|
||||
ram_addr,
|
||||
ram_close,
|
||||
ram_event_bank
|
||||
);
|
||||
|
||||
always @(posedge cb or negedge value) select_out <= cb ? 4'b0000 : 4'b1111;
|
||||
|
||||
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Reference in New Issue
Block a user