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GabrielTofvesson a3f7a48276 Fixed minor issues in ALU.v

Rewrote RAM.v
  RAM should now support read and write
  RAM CKE will be pulled low when no queries to it are being made
  Added bank-independent read/write systems
  Added parameterized per-bank clock-hogging

2018-10-17 02:34:03 +02:00

.gitignore

Added basic VGA graphics support

2018-10-12 16:59:08 +02:00

altpll0_bb.v

Added current Verilog files

2018-10-12 01:23:29 +02:00

altpll0.ppf

Added current Verilog files

2018-10-12 01:23:29 +02:00

altpll0.qip

Added current Verilog files

2018-10-12 01:23:29 +02:00

altpll0.v

Added current Verilog files

2018-10-12 01:23:29 +02:00

ALU.v

Fixed minor issues in ALU.v

2018-10-17 02:34:03 +02:00

Callback.v

Fixed minor issues in ALU.v

2018-10-17 02:34:03 +02:00

Divider.v

Added basic VGA graphics support

2018-10-12 16:59:08 +02:00

FastAdder.py

Added CLA adder circuit generator

2018-10-12 11:39:08 +02:00

FastMath.v

Added basic VGA graphics support

2018-10-12 16:59:08 +02:00

LICENSE

Initial commit

2018-10-12 01:08:09 +02:00

RAM.v

Fixed minor issues in ALU.v

2018-10-17 02:34:03 +02:00

README.md

Initial commit

2018-10-12 01:08:09 +02:00

SegmentHexEncoder.v

Added current Verilog files

2018-10-12 01:23:29 +02:00

SegmentManager.v

Added basic VGA graphics support

2018-10-12 16:59:08 +02:00

SevenSegment.v

Fixed minor issues in ALU.v

2018-10-17 02:34:03 +02:00

VDivider.v

Added current Verilog files

2018-10-12 01:23:29 +02:00

VGA.v

Added shift/rotate operations to ALU

2018-10-15 09:21:03 +02:00

README.md

FreeCPU

A CPU described in HDL for the Cyclone IV EP4CE6E22C8N