GabrielTofvesson
a3f7a48276
Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging
189 lines
7.1 KiB
Verilog
189 lines
7.1 KiB
Verilog
/*
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* DEVICE INFORMATION:
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* HY57V641620FTP-7:
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* RAS latency: 2 or 3 cycles
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* RCD latency: 2 or 3 cycles
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* full address_select available for row selection
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* address_select[7:0] available for col selection
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*/
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module RAM(
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input wire clk, // Clock signal
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output reg [10:0] RAM_addr, // RAM address buffer
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output reg RAM_A10, // RAM address/auto-precharge
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output reg [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output reg RAM_enable, // RAM chip enable
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output reg RAM_strobe_row, // RAM row strobe
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output reg RAM_strobe_col, // RAM column strobe
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output reg RAM_write_enable, // RAM data bus write enable
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input wire read_rq, // Read request (Internal)
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input wire write_rq, // Write request (Internal)
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input wire [1:0] access_bank, // Which bank to access
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output wire op_trigger, // Event trigger wire
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input wire [11:0] address_select, // Address selection when accessing RAM,
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input wire stop_access, // Close a row
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output reg [1:0] op_bank // Bank being accessed when op_trigger is pulled high
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);
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parameter CPB = 4; // Specifies in bit length how many cycles a bank burst can allocate for itself before other banks are checked
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parameter tRCD = 3 + 1; // Assume RCD latency of 3 cycles
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parameter tRAS = 3 + 1; // Assume CAS latency of 3 cycles
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reg [CPB-1:0] acc_cycles; // Cycles used on current bank
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reg [1:0] acc_bank; // Which bank is allocating read cycles
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reg [1:0] acc_close[0:3]; // Requests a close of the current row
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reg [3:0] acc_type; // The current access type of the bank (0: READ, 1: WRITE)
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reg [3:0] acc_state [0:3]; // Current access state for each bank (0: READY, 1: OPENING, 2: tRCD, 3: READ, 4: STOPPING)
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reg [3:0] acc_init_callback; // Pull this high to initiate a callback
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reg [1:0] event_trigger; // Event triggers drive op_trigger
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wire [3:0] acc_event; // Event update callback wire
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wire [2:0] callback_timeout[0:3]; // Callback clock cycle definition
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Callback #(.ISIZE(3)) cb0(clk, callback_timeout[0], acc_init_callback[0], acc_event[0]);
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Callback #(.ISIZE(3)) cb1(clk, callback_timeout[1], acc_init_callback[1], acc_event[1]);
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Callback #(.ISIZE(3)) cb2(clk, callback_timeout[2], acc_init_callback[2], acc_event[2]);
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Callback #(.ISIZE(3)) cb3(clk, callback_timeout[3], acc_init_callback[3], acc_event[3]);
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// Initialize the ram in an inactive state
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initial RAM_enable = 1'b1;
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initial RAM_strobe_row = 1'b1;
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initial RAM_strobe_col = 1'b1;
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initial RAM_write_enable = 1'b1;
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initial acc_bank = 1'b1;
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assign op_trigger = event_trigger[0] ^ event_trigger[1];
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assign RAM_clk = clk;
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assign RAM_clk_enable = (acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]) ? 1'b1 : 1'b0;
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genvar n;
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generate
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for(n = 0; n < 4; n = n + 1) begin : gen_callback_timing
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assign callback_timeout[n] = acc_state[n][1] ? tRAS : tRCD;
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end
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endgenerate
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integer i;
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always @(posedge read_rq or posedge write_rq or posedge acc_event or posedge stop_access or posedge clk) begin
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if(read_rq || write_rq) begin
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if(acc_state[access_bank] == 4'b0000) begin
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RAM_enable <= 1'b0;
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RAM_strobe_row <= 1'b0;
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RAM_strobe_col <= 1'b1;
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RAM_write_enable <= 1'b1;
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RAM_bank_sel <= access_bank;
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RAM_addr <= {address_select[11], address_select[9:0]};
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RAM_A10 <= address_select[10];
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acc_type[access_bank] <= read_rq ? 1'b0 : 1'b1;
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acc_state[access_bank] <= 4'b0001;
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acc_init_callback[access_bank] <= 1'b1;
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acc_close[access_bank] <= 1'b0;
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end
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end
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else if(stop_access) begin
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if(acc_state[access_bank])
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acc_close[access_bank] <= 1'b1;
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end
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else if(clk) begin
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for(i = 0; i < 4; i = i + 1)
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if(acc_state[i] == 4'b0010)
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acc_init_callback[i] <= 1'b1;
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if(~(acc_state[0] | acc_state[1] | acc_state[2] | acc_state[3]))
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RAM_enable <= 1'b1;
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// Bank access management
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acc_cycles[acc_bank] <= acc_cycles[acc_bank] + 1'b1;
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if(acc_cycles[acc_bank] == {CPB{1'b1}}) begin
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// Close banks as needed
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if(acc_close[0]) begin
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acc_close[0] <= 1'b0;
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RAM_bank_sel <= 2'b00;
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acc_state[0] <= 4'b0000;
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end
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else if(acc_close[1]) begin
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acc_close[1] <= 1'b0;
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RAM_bank_sel <= 2'b01;
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acc_state[1] <= 4'b0000;
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end
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else if(acc_close[2]) begin
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acc_close[2] <= 1'b0;
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RAM_bank_sel <= 2'b10;
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acc_state[2] <= 4'b0000;
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end
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else if(acc_close[3]) begin
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acc_close[3] <= 1'b0;
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RAM_bank_sel <= 2'b11;
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acc_state[3] <= 4'b0000;
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end
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// Increment bank tracker
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if(~(acc_close[0] | acc_close[1] | acc_close[2] | acc_close[3])) begin
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acc_bank <= acc_bank + 1;
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acc_cycles <= {CPB{1'b0}};
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end
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else begin
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// Trigger RAM row-close event
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RAM_enable <= 1'b0;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b1;
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RAM_write_enable <= 1'b0;
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end
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end
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else begin
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// Access bank
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for(i = 0; i < 4; i = i + 1) begin
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// Bank_{i} active and not closing and...
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// Enough cycles left or when no other bank is active or...
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// Bank_{i+1} at cycle limit and next banks inactive or bank is closing or...
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// Bank_{i+2} at cycle limit and next bank inactive or bank is closing or...
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// Bank_{i+3} at cycle limit or closing
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if(!acc_close[i] && acc_state[i] == 4'b0100 && (
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(acc_bank == i && (acc_cycles != {CPB{1'b1}} || (acc_state[(i+1)%4] != 4'b0100 && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100))) ||
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(acc_bank == (i+1)%4 && ((acc_close[(i+1)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+2)%4] != 4'b0100 && acc_state[(i+3)%4] != 4'b0100)) ||
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(acc_bank == (i+2)%4 && ((acc_close[(i+2)%4] || acc_cycles == {CPB{1'b1}}) && acc_state[(i+3)%4] != 4'b0100)) ||
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(acc_bank == (i+3)%4 && (acc_close[(i+3)%4] || acc_cycles == {CPB{1'b1}}))
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)) begin
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RAM_bank_sel <= i;
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RAM_addr <= {2'b0, RAM_addr[7:0]};
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RAM_A10 <= 1'b1;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b0;
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RAM_write_enable <= ~acc_type[i];
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op_bank <= i;
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event_trigger[0] <= event_trigger[1] ? 1'b0 : 1'b1;
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end
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end
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end
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end
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else if(acc_event) begin
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for(i = 0; i < 4; i = i + 1) begin
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if(acc_state[i] == 4'b0001) begin
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RAM_bank_sel <= i;
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RAM_strobe_row <= 1'b1;
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RAM_strobe_col <= 1'b0;
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RAM_write_enable <= ~acc_type[i];
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RAM_A10 <= 1;
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acc_state[i] <= 4'b0010;
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acc_init_callback[i] <= 1'b0;
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end
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else if(acc_state[i] == 4'b0010) begin
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acc_init_callback[i] <= 1'b0;
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acc_state[i] <= 4'b0100;
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end
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end
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end
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end
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// Reset op_trigger by tracking posedge-driven event_trigger
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always @(negedge clk) event_trigger[1] <= event_trigger[0] ? 1'b1 : 1'b0;
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endmodule
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