GabrielTofvesson
a3f7a48276
Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging
186 lines
6.5 KiB
Verilog
186 lines
6.5 KiB
Verilog
module SevenSegment(
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input wire latch, // S4
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input wire next, // S2
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input wire value, // S3
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output reg [3:0] select_out, // LED1-LED4 [0-3]
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input wire write, // S1
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input wire clk, // 50MHz clock
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output [3:0] seg_select, // Q1-Q4 [0-3]
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output [7:0] seg_write, // a-g + dp [0-7] + 8
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output reg beep, // Buzzer
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output wire [10:0] RAM_addr, // RAM address buffer
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output wire RAM_A10, // RAM A10 precharge/address
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output wire [1:0] RAM_bank_sel, // RAM bank selection
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inout wire [15:0] RAM_data, // RAM data bus
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output wire RAM_clk, // RAM clock signal
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output wire RAM_clk_enable, // RAM enable clock
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output wire RAM_enable, // RAM chip enable
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output wire RAM_strobe_row, // RAM row strobe
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output wire RAM_strobe_col, // RAM column strobe
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output wire RAM_write_enable, // RAM data bus write enable
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output wire VGA_vsync, // VGA display vsync trigger
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output wire VGA_hsync, // VGA display hsync trigger
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output wire [2:0] VGA_rgb // VGA color channels [0]: RED, [1]: GREEN, [2]: BLUE
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);
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// ---- SETTINGS ---- //
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localparam PLL_SELECT = 1; // 0: 100MHz, 1: 200MHz, 2: 300MHz, 3: 400MHz, 4: 50MHz
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localparam RAM_PLL = 0; // Must be either 0 or 1. DO NOT SET TO ANY OTHER VALUE AS IT MIGHT FRY THE ONBOARD RAM!!!
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// ---- REGISTERS ---- //
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reg debounce; // Input debouncer
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reg db_trap; // Debounce buffer
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reg [3:0] seg_buf_numbers [0:3];// 7-segment binary-number-representation buffer
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reg [1:0] stage; // Computational stage
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reg [7:0] alu_a; // ALU (core0) input a
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reg [7:0] alu_b; // ALU (core0) input b
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reg [7:0] alu_op; // ALU (core0) opcode
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reg [2:0] gfx_rgb; // VGA color channels
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reg [1:0] ram_bank_sel; // Which ram bank to access
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reg [11:0] ram_addr; // RAM address selection
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reg ram_close; // RAM close-row trigger
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// ---- WIRES ---- //
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wire [7:0] seg_buf[0:3]; // Encoded segment buffer (8-bit expanded 4-bit number buffer)
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wire [7:0] alu_out; // ALU (core0) output
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wire [7:0] alu_flags; // ALU (core0) output flags
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wire [4:0] pll; // Phase-locked-loop connections (+ source clock)
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wire vga_clk; // VGA data clock
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wire cb; // Callback/timeout
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wire [9:0] vga_coords[0:1]; // Current screen coordinates being drawn to
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wire ram_request_read; // Trigger a read operation from main memory
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wire ram_request_write; // Trigger a write operation from main memory
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wire ram_event; // Event trigger from ram when a r/w operation is ready
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wire [1:0] ram_event_bank; // Which bank an event is happening on
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// ---- WIRE ASSIGNS ---- //
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assign pll[4] = clk;
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// ---- INITIAL VALUES ---- //
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initial select_out = 4'b1111;
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initial debounce = 1'b0;
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initial db_trap = 1'b1;
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// Hex encoders for each 4-bit input set. Generates an 8-bit hex output
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SegmentHexEncoder enc0(.number (seg_buf_numbers[0]), .encoded (seg_buf[0]));
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SegmentHexEncoder enc1(.number (seg_buf_numbers[1]), .encoded (seg_buf[1]));
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SegmentHexEncoder enc2(.number (seg_buf_numbers[2]), .encoded (seg_buf[2]));
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SegmentHexEncoder enc3(.number (seg_buf_numbers[3]), .encoded (seg_buf[3]));
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// A segment display manager to handle rendering data to the 7-segment displays
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SegmentManager seg_display(
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.clk (clk),
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.segment_data0 (seg_buf[0]),
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.segment_data1 (seg_buf[1]),
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.segment_data2 (seg_buf[2]),
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.segment_data3 (seg_buf[3]),
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.segment_select (seg_select),
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.segments (seg_write)
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);
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// Graphics controller
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VGA screen(clk, gfx_rgb, vga_clk, vga_coords[0], vga_coords[1], VGA_rgb, VGA_hsync, VGA_vsync);
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// Arithmetic logic unit
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ALU #(.BITS(8), .LOG2_BITS(3)) core0(.a(alu_a), .b(alu_b), .op(alu_op), .z(alu_out), .o_flags(alu_flags));
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// Clock generator
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altpll0 pll_gen(clk, pll[0], pll[1], pll[2], pll[3]);
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// Callback module (generate timeouts) (Precision: 1/100M = 10ns) NOTE: 400MHz seems to be unstable, so a precision of 2.5ns comes at the price of stability
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Callback #(.ISIZE(32)) timeout(pll[0], 32'd100000000, ~value, cb);
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// RAM module
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RAM main_memory(
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pll[RAM_PLL],
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RAM_addr,
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RAM_A10,
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RAM_bank_sel,
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RAM_data,
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RAM_clk,
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RAM_clk_enable,
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RAM_enable,
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RAM_strobe_col,
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RAM_strobe_row,
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RAM_write_enable,
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ram_request_read,
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ram_request_write,
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ram_bank_sel,
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ram_event,
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ram_addr,
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ram_close,
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ram_event_bank
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);
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always @(posedge cb or negedge value) select_out <= cb ? 4'b0000 : 4'b1111;
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always @(posedge vga_clk) gfx_rgb <= alu_a[2:0];
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always @(posedge pll[PLL_SELECT]) begin
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if(!latch && write && next) begin
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debounce <= 1'b1;
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end
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if(write && next && db_trap) begin
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debounce <= 1'b0;
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db_trap <= 1'b0;
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end
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if(!write && debounce && !db_trap) begin
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db_trap <= 1'b1;
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if(stage == 2'b0) begin
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alu_a <= alu_a + 8'b1;
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end else if(stage == 2'b1) begin
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alu_b <= alu_b + 8'b1;
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end else if(stage == 2'b10) begin
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alu_op <= alu_op + 8'b1;
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end
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end else if (!next && debounce && !db_trap) begin
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db_trap <= 1'b1;
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stage <= stage + 2'b1;
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if(stage == 2'b01) begin
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seg_buf_numbers[0] <= 4'b0;
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seg_buf_numbers[1] <= 4'b0;
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seg_buf_numbers[2] <= 4'b0;
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seg_buf_numbers[3] <= 4'b0;
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end
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else if(stage == 2'b10) begin
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seg_buf_numbers[0] <= alu_out[7:4];
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seg_buf_numbers[1] <= alu_out[3:0];
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seg_buf_numbers[2] <= alu_flags[7:4];
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seg_buf_numbers[3] <= alu_flags[3:0];
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end
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else if(stage == 2'b11) begin
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seg_buf_numbers[0] <= 4'b0;
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seg_buf_numbers[1] <= 4'b0;
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seg_buf_numbers[2] <= 4'b0;
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seg_buf_numbers[3] <= 4'b0;
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alu_a <= 8'b0;
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alu_b <= 8'b0;
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alu_op <= 8'b0;
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end
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end
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if(stage == 2'b00 || stage == 2'b01) begin
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seg_buf_numbers[0] <= alu_a[7:4];
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seg_buf_numbers[1] <= alu_a[3:0];
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seg_buf_numbers[2] <= alu_b[7:4];
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seg_buf_numbers[3] <= alu_b[3:0];
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end else if(stage == 2'b10) begin
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seg_buf_numbers[0] <= alu_op[7:4];
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seg_buf_numbers[1] <= alu_op[3:0];
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seg_buf_numbers[2] <= 4'b0;
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seg_buf_numbers[3] <= 4'b0;
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end else if(stage == 2'b11) begin
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seg_buf_numbers[0] <= alu_out[7:4];
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seg_buf_numbers[1] <= alu_out[3:0];
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seg_buf_numbers[2] <= alu_flags[7:4];
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seg_buf_numbers[3] <= alu_flags[3:0];
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end
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//select_out[0] <= ~debounce;
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//select_out[1] <= write;
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//select_out[2] <= next;
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//select_out[3] <= latch;
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end
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endmodule
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