4 Commits

Author	SHA1	Message	Date
GabrielTofvesson	635158444b	Replaced tabs with spaces	2018-10-17 02:38:17 +02:00
GabrielTofvesson	a3f7a48276	Fixed minor issues in ALU.v ... Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging	2018-10-17 02:34:03 +02:00
GabrielTofvesson	026def0a26	Changed clock source for test callback module due to stability issues	2018-10-15 09:27:23 +02:00
GabrielTofvesson	41f95d2077	Added shift/rotate operations to ALU ... Added callback/timeout module Added pixel location output to VGA module Fixed state management for RAM module Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable	2018-10-15 09:21:03 +02:00