GabrielTofvesson/FreeCPU
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Author SHA1 Message Date
GabrielTofvesson
41f95d2077 Added shift/rotate operations to ALU 
Added callback/timeout module
Added pixel location output to VGA module
Fixed state management for RAM module
Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable
 2018-10-15 09:21:03 +02:00
GabrielTofvesson
4642890198 Continued implementing RAM module 
Added VGA test to project
 2018-10-12 23:27:25 +02:00
GabrielTofvesson
8b9bd6e106 Added basic VGA graphics support 
Generated some basic FastAdders
Generalized FastAdder to include all fast math modules
Other minor changes
 2018-10-12 16:59:08 +02:00
GabrielTofvesson
571a280d3e Added CLA adder circuit generator 2018-10-12 11:39:08 +02:00
GabrielTofvesson
1126ce5582 Added current Verilog files 2018-10-12 01:23:29 +02:00
Gabriel Tofvesson
4f1a53847c
Initial commit 2018-10-12 01:08:09 +02:00