GabrielTofvesson/FreeCPU
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Author SHA1 Message Date
GabrielTofvesson
a3f7a48276 Fixed minor issues in ALU.v 
Rewrote RAM.v
  RAM should now support read and write
  RAM CKE will be pulled low when no queries to it are being made
  Added bank-independent read/write systems
  Added parameterized per-bank clock-hogging
 2018-10-17 02:34:03 +02:00
Gabriel Tofvesson
7ebac10ffc
Delete SDRAM.v 2018-10-15 11:35:38 +02:00
GabrielTofvesson
10d33a514f Made ALU parameter bit width variable 
Removed CL_MUL operation due to complications with variable-sized inputs
Fixed RAM implementation issues
 2018-10-15 11:34:50 +02:00
GabrielTofvesson
30ceb1f2ce Started implementing RAM bank parallelization 2018-10-15 09:47:11 +02:00
GabrielTofvesson
026def0a26 Changed clock source for test callback module due to stability issues 2018-10-15 09:27:23 +02:00
GabrielTofvesson
41f95d2077 Added shift/rotate operations to ALU 
Added callback/timeout module
Added pixel location output to VGA module
Fixed state management for RAM module
Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable
 2018-10-15 09:21:03 +02:00
GabrielTofvesson
4642890198 Continued implementing RAM module 
Added VGA test to project
 2018-10-12 23:27:25 +02:00
GabrielTofvesson
8b9bd6e106 Added basic VGA graphics support 
Generated some basic FastAdders
Generalized FastAdder to include all fast math modules
Other minor changes
 2018-10-12 16:59:08 +02:00
GabrielTofvesson
571a280d3e Added CLA adder circuit generator 2018-10-12 11:39:08 +02:00
GabrielTofvesson
1126ce5582 Added current Verilog files 2018-10-12 01:23:29 +02:00
Gabriel Tofvesson
4f1a53847c
Initial commit 2018-10-12 01:08:09 +02:00