8 Commits

Author	SHA1	Message	Date
GabrielTofvesson	8472077a4b	Fixed comments ... Losslessly truncated register	2018-10-17 02:46:27 +02:00
GabrielTofvesson	635158444b	Replaced tabs with spaces	2018-10-17 02:38:17 +02:00
GabrielTofvesson	a3f7a48276	Fixed minor issues in ALU.v ... Rewrote RAM.v RAM should now support read and write RAM CKE will be pulled low when no queries to it are being made Added bank-independent read/write systems Added parameterized per-bank clock-hogging	2018-10-17 02:34:03 +02:00
GabrielTofvesson	10d33a514f	Made ALU parameter bit width variable ... Removed CL_MUL operation due to complications with variable-sized inputs Fixed RAM implementation issues	2018-10-15 11:34:50 +02:00
GabrielTofvesson	30ceb1f2ce	Started implementing RAM bank parallelization	2018-10-15 09:47:11 +02:00
GabrielTofvesson	41f95d2077	Added shift/rotate operations to ALU ... Added callback/timeout module Added pixel location output to VGA module Fixed state management for RAM module Lowered clock speed for circuit to 200MHz because 400MHz was unstable. NOTE: even 200MHz is quite unstable	2018-10-15 09:21:03 +02:00
GabrielTofvesson	4642890198	Continued implementing RAM module ... Added VGA test to project	2018-10-12 23:27:25 +02:00
GabrielTofvesson	1126ce5582	Added current Verilog files	2018-10-12 01:23:29 +02:00